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    • 61. 发明授权
    • Semiconductor memory device provided with error correcting code circuitry
    • 具有纠错码电路的半导体存储器件
    • US07225390B2
    • 2007-05-29
    • US10617040
    • 2003-07-11
    • Yutaka ItoKiyoshi Nakai
    • Yutaka ItoKiyoshi Nakai
    • H03M13/00
    • G11C11/40615G06F11/1012G11C11/406G11C2211/4062
    • A semiconductor synchronous dynamic random access memory (SDRAM) device capable of correcting bits having a low error rate in a Pause Refresh Tail distribution and of reducing a data holding current by lengthening a refresh period so that the refresh period exceeds a period for a Pause Refresh real power. The semiconductor memory device is made up of a 16-bit SDRAM having a Hamming Code and including an ECC (Error Correcting Code) circuit made up of an encoding circuit controlled by a first test signal to output a parity bit corresponding to an information bit, a decoding circuit controlled by second test signal to output an error location detecting signal indicating an error bit in codeword, and an error correcting circuit controlled by a third test signal to input an error location detecting signal and to output an error bit in a reverse manner.
    • 一种半导体同步动态随机存取存储器(SDRAM)装置,其能够在暂停刷新尾部分配中校正具有低错误率的比特,并且通过延长刷新周期来减少数据保持电流,使得刷新周期超过暂停刷新的周期 真正的权力。 半导体存储器件由具有汉明码的16位SDRAM构成,并包括由第一测试信号控制的编码电路组成的ECC(纠错码)电路,以输出对应于信息位的奇偶位, 由第二测试信号控制的解码电路,以输出指示码字中的错误位的错误位置检测信号,以及由第三测试信号控制的纠错电路,以输入错误位置检测信号并以相反的方式输出错误位 。
    • 62. 发明申请
    • Membrane separation device and membrane separation method
    • 膜分离装置和膜分离方法
    • US20050126966A1
    • 2005-06-16
    • US10514621
    • 2003-05-14
    • Katsuyoshi TanidaShinichi NonakaMitsushige ShimadaTsutomu MatsudaKiyoshi HiraiMasahiro UemuraKazutaka TakataYutaka ItoSusumu Hasegawa
    • Katsuyoshi TanidaShinichi NonakaMitsushige ShimadaTsutomu MatsudaKiyoshi HiraiMasahiro UemuraKazutaka TakataYutaka ItoSusumu Hasegawa
    • B01D63/08B01D65/00B01D65/02B01D69/06C02F1/44B01D63/00
    • B01D65/00B01D63/084B01D65/003B01D69/06B01D2313/04B01D2313/143B01D2319/022C02F1/444
    • It is an object of the present invention to provide a membrane separation apparatus and a membrane separation process that are unlikely to cause membrane fouling and plugging, capable of achieving membrane separation even with relatively low flow rate of water, have an excellent membrane packing density, and are unlikely to cause deposition of foreign components in the apparatus. In order to achieve the above object, according to the present invention, vessel-type inner casings are disposed in a pressure vessel along the longitudinal axis thereof, in which the pressure vessel has a water inlet at a first end and a concentrate outlet at a second end. A flow-regulating plate is disposed on the side of the water inlet of the pressure vessel. Stacks of membrane separation units are respectively disposed in the inner casings, and spacers are disposed between the adjacent membrane separation elements. The spacers also serve as sealing members. Each stack of the membrane separation units and the spacers together define a through-hole extending from a first side to a second side, of the stack of the membrane separation elements. The inner casings have permeate discharge passages along the longitudinal axis thereof. The permeate discharge passages are communicated with the through-hole of each stack of the membrane separation elements. Water that has been fed into the pressure vessel via the flow-regulating plate permeates through the membrane separation elements and is discharged to the outside via the through-holes and the permeate discharge passages.
    • 本发明的目的是提供即使在相对较低的水流速下也能够实现膜分离的膜分离装置和膜分离方法不易引起膜污染和堵塞,具有优异的膜堆积密度, 并且不太可能引起异物在设备中的沉积。 为了实现上述目的,根据本发明,容器式内壳沿其纵向轴线设置在压力容器中,其中压力容器在第一端具有进水口和在第一端处具有浓缩物出口 第二端 流量调节板设置在压力容器的入口侧。 膜分离单元的分隔件分别设置在内壳中,间隔件设置在相邻的膜分离元件之间。 间隔件还用作密封构件。 膜分离单元和间隔物的每一叠层一起限定了从膜分离元件的堆叠的第一侧延伸到第二侧的通孔。 内壳具有沿其纵向轴线的渗透物排出通道。 渗透物排出通道与膜分离元件的每个叠层的通孔连通。 已经通过流量调节板进入压力容器的水渗入膜分离元件,并经由通孔和渗透物排出通道排出到外部。
    • 64. 发明授权
    • Method of deciding error rate and semiconductor integrated circuit device
    • 决定误码率的方法和半导体集成电路器件
    • US06735726B2
    • 2004-05-11
    • US09875961
    • 2001-06-08
    • Masaya MuranakaHideaki KatoYutaka Ito
    • Masaya MuranakaHideaki KatoYutaka Ito
    • G06F1100
    • G06F11/1008G06F2201/88G06F2211/109G11C7/1006G11C29/42
    • There is provided an error rate select circuit activated in an information sustaining mode, wherein data is read out from a memory circuit comprising dynamic memory cells and inspection bits for detection and correction of an error. If no error is detected, a first detection signal is accumulated in a first direction, that is, the first detection signal is added to a sum. If an error is detected, a second detection signal is accumulated in a second direction, that is, the second direction signal is multiplied by a weight to produce a product before subtracting the product from the sum. If the sum increases in the first direction, exceeding a predetermined value, the refresh period is lengthened by a predetermined incremental time. If the sum decreases in the second direction, becoming smaller than another predetermined value, the refresh period is shortened by a predetermined decremental time.
    • 提供了在信息维持模式下激活的错误率选择电路,其中从包括动态存储单元的存储器电路和检查位读出数据,以检测和校正错误。 如果没有检测到错误,则在第一方向上累积第一检测信号,即,将第一检测信号加到和。 如果检测到错误,则在第二方向上累积第二检测信号,即,将第二方向信号乘以权重,以产生从总和中减去乘积之前的乘积。 如果总和在第一方向上增加超过预定值,则刷新周期被延长预定的增量时间。 如果总和在第二方向上减小,变得小于另一个预定值,则刷新周期被缩短预定的递减时间。
    • 66. 发明授权
    • Lubricant, magnetic disk and magnetic disk apparatus
    • 润滑剂,磁盘和磁盘装置
    • US06555197B1
    • 2003-04-29
    • US09561216
    • 2000-04-28
    • Mina IshidaTakayuki NakakawajiYutaka ItoHiroyuki MatsumotoHiroshi TaniHeigo Ishihara
    • Mina IshidaTakayuki NakakawajiYutaka ItoHiroyuki MatsumotoHiroshi TaniHeigo Ishihara
    • G11B5725
    • G11B5/725G11B5/71G11B33/148Y10T428/3154
    • A lubricant which does not splash easily and has an improved property of slidableness, and a magnetic disk using the lubricant are provided. A magnetic disk apparatus featuring a prolonged service life of a stable operation and an excellent record reproduction property is provided by installing the above magnetic disk. The lubricant of the invention contains perfluoropolyether expressed by the following general formula, in which a component of its molecular weights less than 1000 is smaller than 10 wt. %, a component of its molecular weights not less than 7000 is smaller than 15 wt. %, a ratio between a weight average molecular weight and a numeric average molecular weight is 1.5 or less, and a substitution ratio of its terminal functional group is not less than 90%: R1—CF2O—[—(CF2CF2O )—m—(CF2O)—n—]—CF2—R2  (1), where R1 and R2 are univalent organic groups, m and n are positive integers. Further for the magnetic disk which rotates at a speed of 10000 rpm or more, a lubricant containing a perfluoropolyether expressed by the following general formula is used, in which its numeric average molecular weight is not less than 5500, a component of molecular weights less than 3000 is 15 wt. % or less, a ratio between its weight average molecular weight and its numeric average molecular weight is 1.5 or less, and a substitution ratio of its terminal functional group is not less than 90%: HOCH2—CF2O—[—CF2CF2O]—m—[CF2O]—n—CF2—CH2OH  (2), where m and n are positive integers.
    • 提供不容易飞溅并且具有改善的滑动性的润滑剂和使用润滑剂的磁盘。 通过安装上述磁盘来提供具有延长的稳定操作的使用寿命和良好的记录再现性能的磁盘装置。 本发明的润滑剂包含由以下通式表示的全氟聚醚,其中分子量小于1000的组分小于10重量%。 %,其分子量不小于7000的组分小于15重量%。 %,重均分子量与数均分子量之比为1.5以下,其末端官能团的取代率为90%以上:其中,R1和R2为单价有机基团,m和n为 正整数。 此外,对于以10000rpm以上的速度旋转的磁盘,使用含有由以下通式表示的全氟聚醚的润滑剂,其数均分子量不小于5500,分子量小于 3000是15wt。 %以下,其重均分子量与数均分子量之比为1.5以下,其末端官能团的取代率为90%以上:m和n为正整数。
    • 68. 再颁专利
    • ATM switching system connectable to I/O links having different
transmission rates
    • ATM交换系统可连接到具有不同传输速率的I / O链路
    • USRE36751E
    • 2000-06-27
    • US430802
    • 1995-04-26
    • Takahiko KozakiJunichirou YanagiKiyoshi AikiYutaka ItoKaoru AokiShinobu Gohara
    • Takahiko KozakiJunichirou YanagiKiyoshi AikiYutaka ItoKaoru AokiShinobu Gohara
    • H04J3/24H04L12/56H04Q11/04
    • H04Q11/0478H04J3/247H04L12/5601H04L12/5602H04L45/04H04L49/108H04L49/256H04L49/3081H04L2012/5627H04L2012/5651H04L2012/5652H04L2012/5672H04L2012/5681
    • An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
    • ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元,以及多路复用器,用于将从至少两个输出端口输出的单元列复用为单个单元列,并输出该单元 训练到高速输出线(和/或解复用器,用于从输出端口多路复用到多个单元列,并将单元列输出到多个低速输出线)。 开关单元包括缓冲存储器,用于临时存储从输入端口输入的单元,同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器,用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路,用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置,并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。
    • 69. 发明授权
    • Method of fabricating a high-density dynamic random-access memory
    • 制造高密度动态随机存取存储器的方法
    • US5856219A
    • 1999-01-05
    • US912686
    • 1997-08-18
    • Yasushi NaitoYutaka ItoYuichi Hirofuji
    • Yasushi NaitoYutaka ItoYuichi Hirofuji
    • H01L23/522H01L21/768H01L21/8239H01L21/8242H01L27/10H01L27/108
    • H01L27/1052H01L27/10873
    • The invention relates to a high-density DRAM fabrication technique for forming a source/drain contact between word lines in a self-alignment manner, with the offset length between a source region and a drain region of a peripheral transistor maintained at an adequate value. After gate electrodes (i.e. word lines) are formed, a first insulating layer, which is thin enough not to block up space defined between the word lines, is deposited. The source/drain contact is etched as deep as the first insulating layer is thick to form an extraction electrode made of polycrystalline silicon. A second insulating layer is deposited until a spacer thickness (i.e. the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer) for determining the offset length is obtained. The first and second insulating layers are etched back for a distance corresponding to the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer so that a spacer (i.e. the residue of the insulating layers) is left on the side walls of the gate electrode. An implantation of highlevel impurities is performed to form heavily doped source and drain regions of a peripheral transistor. In-cell self-align contact is made possible while maintaining the offset length of the heavily doped source and drain regions
    • 本发明涉及用于以自对准方式在字线之间形成源极/漏极接触的高密度DRAM制造技术,其中外围晶体管的源极区域和漏极区域之间的偏移长度保持在足够的值。 在形成栅电极(即字线)之后,沉积足够薄而不能阻挡字线之间限定的空间的第一绝缘层。 源极/漏极接触被蚀刻为第一绝缘层较厚的深度,以形成由多晶硅制成的引出电极。 沉积第二绝缘层,直到获得用于确定偏移长度的间隔物厚度(即第二绝缘层的膜厚度和第一绝缘层的膜厚度之和)。 第一绝缘层和第二绝缘层被回蚀一段对应于第二绝缘层的膜厚度与第一绝缘层的膜厚之和的距离,使得间隔物(即,绝缘层的残留物)留在 栅电极的侧壁。 执行高级杂质的注入以形成外围晶体管的重掺杂源极和漏极区域。 在保持重掺杂源极和漏极区域的偏移长度的同时使单元内自对准接触成为可能