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    • 67. 发明授权
    • Processes for the production of thienopyrimidine derivatives
    • 噻吩并嘧啶衍生物的制备方法
    • US06849738B2
    • 2005-02-01
    • US10220233
    • 2001-02-27
    • Koichiro FukuokaHiroaki YamamotoKazuhiro KimuraJunichi KawakamiShokyo Miki
    • Koichiro FukuokaHiroaki YamamotoKazuhiro KimuraJunichi KawakamiShokyo Miki
    • C07D333/38C07D495/04
    • C07D495/04C07D333/38
    • The present invention provides a process for producing an intermediate for thienopyrimidine derivatives having the GnRH antagonistic activity at an industrial large scale.The process for production of the present invention relates to a process for producing a compound represented by the formula (III): wherein respective symbols have the same meanings as those described below, or a salt thereof, which comprises subjecting a compound represented by the formula (I): wherein R1 denotes hydrogen, nitro, halogen, phthalimido, mono- or di-(alkylcarbonyl)amino or alkoxy, or a salt thereof, to an acid halogenating reaction, which is successively reacted with malonic acid ester and magnesium alkoxide, treated with an acid, and reacted with sulfur and a compound represented by the formula: NCCH2COOR2 [wherein R2 denotes alkyl or aryl], or a salt thereof, in the presence of primary amine. According to the process of production of the present invention, thienopyrimidine derivatives having the GnRH antagonistic activity can be produced effectively and at an industrial large scale by a high yield and simple method.
    • 本发明提供了一种在工业上大规模生产具有GnRH拮抗活性的噻吩并嘧啶衍生物的中间体的方法。本发明的制备方法涉及一种由式(III)表示的化合物的制备方法:其中各自 符号具有与下述相同的含义或其盐,其包括使由式(I)表示的化合物:其中R 1表示氢,硝基,卤素,苯二甲酰亚氨基,单 - 或二 - (烷基羰基) 氨基或烷氧基或其盐与酸卤化反应反应,该酸卤化反应与丙酸和烷氧基镁连续反应,用酸处理,并与硫和式NCCH 2 COOR 2表示的化合物反应[其中 R 2表示烷基或芳基]或其盐,在伯胺的存在下。 根据本发明的制造方法,可以通过高产率和简单的方法有效地以工业规模生产具有GnRH拮抗活性的噻吩并嘧啶衍生物。
    • 68. 发明授权
    • Synchronous circuit of FM multiplex broadcasting receiver
    • FM多重广播接收机同步电路
    • US06560207B1
    • 2003-05-06
    • US09255525
    • 1999-02-22
    • Kazuhiro KimuraYutaka Hirakoso
    • Kazuhiro KimuraYutaka Hirakoso
    • H04L700
    • H04H40/18H04H20/55H04H60/70
    • Data counters and perform a counting operation which is synchronized with the respective timing of receiving multiplex data from a VICS data broadcasting station and a D-GPS data broadcasting station. While receiving the multiplex data from the VICS data broadcasting station, based on an output C2 of the data counter and a BIC detection output BP, block synchronization is detected. When the broadcasting station is switched from the VICS data broadcasting station to the D-GPS data broadcasting station, an output C2 of the data counter is selected in response to a control signal CONT and block synchronization is detected based on an output C2 and an output BP. Further, an output C1 is always inputted to the block counter. Thus, even while receiving the multiplex data from the D-GPS data broadcasting station, frame synchronization of the multiplex data of the VICS data broadcasting station is detected without causing miscounting.
    • 数据计数器并执行与从VICS数据广播站和D-GPS数据广播站接收多路复用数据的相应定时同步的计数操作。 在从VICS数据广播站接收多路复用数据的同时,基于数据计数器的输出C2和BIC检测输出BP,检测块同步。 当广播站从VICS数据广播站切换到D-GPS数据广播站时,响应于控制信号CONT选择数据计数器的输出C2,并且基于输出C2和输出来检测块同步 BP。 此外,输出C1总是输入到块计数器。 因此,即使在从D-GPS数据广播站接收多路复用数据的同时,也可以检测VICS数据广播电台的复用数据的帧同步,而不会造成错误计数。
    • 69. 发明授权
    • Error correction device
    • 纠错装置
    • US6017146A
    • 2000-01-25
    • US654859
    • 1996-05-29
    • Takahiko MasumotoSyugo YamashitaKazuhiro KimuraHiroshi Kaneko
    • Takahiko MasumotoSyugo YamashitaKazuhiro KimuraHiroshi Kaneko
    • H04H40/18H03M13/00
    • H04H40/18H04H2201/13
    • A demodulating circuit demodulates a received signal, and outputs patterns of demodulated data and reliability information bits indicating correctness of the demodulated data. These are supplied to first and second shift registers (4 and 5), respectively. When the number of reliability information bits of Level 1 in the second shift register is a predetermined value or less, a shift operation is repeated a plurality of times. When a reliability information bit of Level 1 is outputted, an error correction control circuit (7) successively outputs all possible bit patterns of the demodulated data An EXOR gate (10) generates all possible patterns of demodulated data An error correcting circuit (11) carries out error correction for all the patterns. When the number is larger than the predetermined value, the error correction is carried out only for the demodulated data supplied from the demodulating circuit in a conventional manner.
    • 解调电路对接收到的信号进行解调,并且输出解调数据的模式和指示解调数据的正确性的可靠性信息比特。 这些分别被提供给第一和第二移位寄存器(4和5)。 当第二移位寄存器中的级别1的可靠性信息位的数量是预定值或更小时,多次重复移位操作。 当输出级别1的可靠性信息位时,纠错控制电路(7)连续地输出解调数据的所有可能的位模式。EXOR门(10)产生解调数据的所有可能的模式。纠错电路(11) 出错纠正所有的模式。 当该数量大于预定值时,仅对于从解调电路以常规方式提供的解调数据进行纠错。