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61. 发明授权

US6163045A Reduced parasitic leakage in semiconductor devices 有权
标题翻译：减少半导体器件中的寄生泄漏
公开(公告)号：US6163045A
公开(公告)日：2000-12-19
申请号：US215011
申请日：1998-12-17
申请人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
发明人： Jack A. Mandelman , Louis L. C. Hsu , Johann Alsmeier , William R. Tonti
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10829
摘要： A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.
摘要翻译：一种沟槽式电容器，其具有与该套环相邻的扩散区域以增加寄生MOSFET的栅极阈值电压。这使得能够使用更薄的套环，同时仍然实现可接受的泄漏。在一个实施例中，扩散区域是自对准的。

62. 发明授权

US5894152A SOI/bulk hybrid substrate and method of forming the same 失效
公开(公告)号：US5894152A
公开(公告)日：1999-04-13
申请号：US878225
申请日：1997-06-18
申请人： Mark A. Jaso , Jack A. Mandelman , William R. Tonti , Matthew R. Wordeman
发明人： Mark A. Jaso , Jack A. Mandelman , William R. Tonti , Matthew R. Wordeman
IPC分类号： H01L21/20 , H01L21/76 , H01L21/762 , H01L21/84 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/84 , H01L21/7624 , H01L27/1203
摘要： A semiconductor device having areas that are semiconductor on insulator ("SOI") and areas that are bulk, single crystalline semiconductive areas is provided in which conductive spacers may be formed to electrically connect the SOI areas to ground in order to overcome floating body effects that can occur with SOI. Additionally, insulative spacers may be formed on the surface of the conductive spacers to electrically isolate the SOI regions from the bulk regions. A novel method for making both of these products is provided in which the epitaxially grown, single crystalline bulk regions need not be selectively grown, because a sacrificial polishing layer is deposited, is also provided.

63. 发明授权

US07977766B2 Trench anti-fuse structures for a programmable integrated circuit 有权
标题翻译：用于可编程集成电路的沟槽反熔丝结构
公开(公告)号：US07977766B2
公开(公告)日：2011-07-12
申请号：US12537473
申请日：2009-08-07
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/00 , H01L23/535
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate.
摘要翻译：沟槽反熔丝结构，设计结构体现在用于设计，制造或测试可编程集成电路的机器可读介质中。反熔丝结构包括具有延伸到衬底中的多个侧壁的沟槽，靠近沟槽侧壁的衬底的半导体材料中的掺杂区域，沟槽中的导电插塞以及沟槽中的介电层沟槽的侧壁。电介质层设置在导电插塞和掺杂区域之间。电介质层被配置为使得施加在掺杂区域和导电插塞之间的编程电压导致沟槽区域内的电介质层的击穿。沟槽侧壁布置成具有与深沟槽的底壁和基板的顶表面之间的位置无关的横截面几何形状。

64. 发明申请

US20090147568A1 Memory Elements and Methods of Using the Same 有权
标题翻译：内存元素及其使用方法
公开(公告)号：US20090147568A1
公开(公告)日：2009-06-11
申请号：US12351872
申请日：2009-01-12
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

65. 发明申请

US20080258857A1 ELECTRONIC FUSE WITH CONFORMAL FUSE ELEMENT FORMED OVER A FREESTANDING DIELECTRIC SPACER 失效
标题翻译：具有合适的保险丝元件的电子保险丝在自动电介质间隔件上形成
公开(公告)号：US20080258857A1
公开(公告)日：2008-10-23
申请号：US12128100
申请日：2008-05-28
申请人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
IPC分类号： H01H85/08
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

66. 发明申请

US20080144252A1 PROGRAMMABLE CAPACITORS AND METHODS OF USING THE SAME 审中-公开
标题翻译：可编程电容器及其使用方法
公开(公告)号：US20080144252A1
公开(公告)日：2008-06-19
申请号：US12037725
申请日：2008-02-26
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： H01G7/00
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调整半导体器件的电容的方法。第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。提供了许多其他方面。

67. 发明申请

US20080006855A1 CMOS Devices Adapted to Prevent Latchup and Methods of Manufacturing the Same 失效
标题翻译： CMOS器件适用于防止滞后及其制造方法
公开(公告)号：US20080006855A1
公开(公告)日：2008-01-10
申请号：US11456357
申请日：2006-07-10
申请人： Jack A. Mandelman , William R. Tonti
发明人： Jack A. Mandelman , William R. Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L21/743 , H01L21/823814 , H01L21/823878 , H01L27/0921 , H01L29/665 , H01L2027/1189
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (3) a conductive region that electrically couples a source diffusion region of the first or second MOSFET with a doped well region below the source diffusion region. The conductive region is adapted to prevent an induced current from forming in the loop. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是衬底上的半导体器件，其包括：（1）第一金属氧化物半导体场效应晶体管（MOSFET）; （2）耦合到所述第一MOSFET的第二MOSFET，其中所述第一和第二MOSFET的部分形成耦合到环路中的第一和第二双极结型晶体管（BJT）; 和（3）将第一或第二MOSFET的源极扩散区域与源极扩散区域下方的掺杂阱区域电耦合的导电区域。导电区域适于防止在环路中形成感应电流。提供了许多其他方面。

68. 发明授权

US06869846B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
标题翻译：形成具有双介电厚度的电子结构和如此形成的结构
公开(公告)号：US06869846B2
公开(公告)日：2005-03-22
申请号：US10411850
申请日：2003-04-10
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.
摘要翻译：一种包括第一装置和第二装置的结构，其中所述第二装置的电介质厚度大于所述第一装置的电介质厚度，以及形成所述结构的方法。

69. 发明授权

US06724029B2 Twin-cell flash memory structure and method 有权
标题翻译：双电池闪存结构及方法
公开(公告)号：US06724029B2
公开(公告)日：2004-04-20
申请号：US09683831
申请日：2002-02-21
申请人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115
摘要： A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.
摘要翻译：提供了包括一对存储单元的可编程存储单元结构。每对存储单元包括共享控制栅极和围绕共享控制栅极存在的第一和第二浮动栅极。第一和第二浮栅具有设置在控制栅极的相应侧上的各自的栅极区域。电介质结构存在于控制栅极和浮动栅极的各个栅极区域之间。第一和第二浮动栅极的控制栅极和栅极形成在单个光刻平面内。

70. 发明授权

US06566191B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US06566191B2
公开(公告)日：2003-05-20
申请号：US09731148
申请日：2000-12-05
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L218242
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

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