专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20080151672A1 DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE 有权
标题翻译：基于充电储存装置的可能性确定使用数据保留装置的相对数量
公开(公告)号：US20080151672A1
公开(公告)日：2008-06-26
申请号：US12045744
申请日：2008-03-11
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G11C7/00
CPC分类号： G06F12/121 , G06F12/122
摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.
摘要翻译：公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

62. 发明申请

US20080148204A1 Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees 失效
公开(公告)号：US20080148204A1
公开(公告)日：2008-06-19
申请号：US11610963
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

63. 发明授权

US07373567B2 System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA 有权
标题翻译：使用嵌入式FPGA的冗余逻辑单元在集成电路中提供错误检测和校正能力的系统和方法
公开(公告)号：US07373567B2
公开(公告)日：2008-05-13
申请号：US10709754
申请日：2004-05-26
申请人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
发明人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/318558 , G06F11/261 , H03K19/00392
摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic function, such that logic EC is provided within the embedded FPGA structure of the IC chip.
摘要翻译：一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。识别故障逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑功能的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。

64. 发明授权

US07362138B1 Flexible multimode logic element for use in a configurable mixed-logic signal distribution path 有权
标题翻译：灵活的多模逻辑元件用于可配置的混合逻辑信号分配路径
公开(公告)号：US07362138B1
公开(公告)日：2008-04-22
申请号：US11613516
申请日：2006-12-20
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/0175
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K19/0016 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路。特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

65. 发明申请

US20080046772A1 SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION 审中-公开
标题翻译：改变噪声减少的不活动时钟边缘
公开(公告)号：US20080046772A1
公开(公告)日：2008-02-21
申请号：US11457916
申请日：2006-07-17
申请人： Igor Arsovski , Joseph A. Iadanza , Jason M. Norman , Hemen Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Joseph A. Iadanza , Jason M. Norman , Hemen Shah , Sebastian T. Ventrone
IPC分类号： G06F1/00
CPC分类号： G06F1/10
摘要： A method and system for reducing clock noises are disclosed. A clock signal includes active edges and inactive edges. Inactive edges produce clock noise but are not critical to the functionality of the clock signal. That is, only active edges are critical to proper timing of an integrated circuit (IC). As such, inactive edges of clock signals to clocked elements of an IC may be shifted to be misaligned to one another. As a consequence, peak noise produced by the inactive edges will be spread over a large area and therefore will be reduced in amplitude.
摘要翻译：公开了一种减少时钟噪声的方法和系统。时钟信号包括有效边沿和非活动边沿。无效边沿产生时钟噪声，但并不对时钟信号的功能至关重要。也就是说，只有有效边沿对于集成电路（IC）的正确定时至关重要。因此，到IC的时钟元件的时钟信号的无效边沿可能被移位以彼此不对准。结果，由无源边缘产生的峰值噪声将在大面积上扩展，因此幅度将被减小。

66. 发明申请

US20070294519A1 Localized Control Caching Resulting In Power Efficient Control Logic 审中-公开
标题翻译：本地控制缓存导致功率有效控制逻辑
公开(公告)号：US20070294519A1
公开(公告)日：2007-12-20
申请号：US11424943
申请日：2006-06-19
申请人： Laura F. Miller , Pascal A. Nsame , Nancy H. Pratt , Sebastian T. Ventrone
发明人： Laura F. Miller , Pascal A. Nsame , Nancy H. Pratt , Sebastian T. Ventrone
IPC分类号： G06F9/44
CPC分类号： G06F9/325 , G06F9/3808 , G06F9/381
摘要： An integrated circuit (IC) including a decoder decoding instructions, shadow latches storing instructions as a localized loop, and a state machine controlling the decoder and the plurality of shadow latches. When the state machine identifies instructions that are the same as those stored in the localized loop, it deactivates the decoder and activates the plurality of shadow latches to retrieve and execute the localized loop in place of the instructions provided by the decoder. Additionally, a method of providing localized control caching operations in an IC to reduce power dissipation is provided. The method includes initializing a state machine to control the IC, providing a plurality of shadow latches, decoding a set of instructions, detecting a loop of decoded instructions, caching the loop of decoded instructions in the shadow latches as a localized loop, detecting a loop end signal for the loop and stopping the caching of the localized loop.
摘要翻译：包括解码指令，存储指令作为局部回路的阴影锁存器的集成电路（IC）以及控制解码器和多个阴影锁存器的状态机。当状态机识别与存储在本地化环路中的指令相同的指令时，其取消对解码器的激活，并激活多个阴影锁存器来取代并执行本地化的循环，代替解码器提供的指令。另外，提供了一种在IC中提供局部控制高速缓存操作以减少功耗的方法。该方法包括初始化状态机以控制IC，提供多个阴影锁存器，解码一组指令，检测解码指令的循环，将阴影锁存器中的解码指令的循环缓存为局部循环，检测循环循环结束信号，并停止局部循环的缓存。

67. 发明授权

US07287177B2 Digital reliability monitor having autonomic repair and notification capability 有权
标题翻译：数字可靠性监控器具有自主修复和通知功能
公开(公告)号：US07287177B2
公开(公告)日：2007-10-23
申请号：US10729751
申请日：2003-12-04
申请人： Anthony R. Bonaccio , Michael LeStrange , William R. Tonti , Sebastian T. Ventrone
发明人： Anthony R. Bonaccio , Michael LeStrange , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G06F1/04 , G07C3/04
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译：一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号的周期的周期计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。

68. 发明授权

US07286770B2 Fiber optic transmission lines on an SOC 失效
标题翻译：光纤传输线上的SOC
公开(公告)号：US07286770B2
公开(公告)日：2007-10-23
申请号：US10604410
申请日：2003-07-18
申请人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
发明人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
IPC分类号： H04B10/00
CPC分类号： G02B6/43
摘要： Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.
摘要翻译：公开了一种集成电路，其包括附接到至少一个发射机和接收机的多个核心，嵌入在集成电路的有线电平内的光传输网络，并且其中发射机和接收机在网络上发送和接收数据。还公开了一种在包括多个核心和光路的集成电路的集成电路内传输信号的方法，从多个光路中选择用于发送数据的光路，以及在所选择的光路上发送数据。还公开了一种集成电路，其包括光传输网络，多个核心和多个控制器，所有三个可操作地彼此连接。

69. 发明授权

US07218135B2 Method and apparatus for reducing noise in a dynamic manner 有权
标题翻译：以动态方式降低噪音的方法和装置
公开(公告)号：US07218135B2
公开(公告)日：2007-05-15
申请号：US11163015
申请日：2005-09-30
申请人： Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone
发明人： Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/00346
摘要： An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.
摘要翻译：集成电路设备包括功能逻辑，抗噪声机器和状态监测点，其为抗噪声机器提供与用于监视功能逻辑状态的功能逻辑的接口。抗噪声机器包括定义用于功能逻辑的噪声前导状态的标记，以及耦合到状态监测点的识别逻辑。抗噪声机器可操作以响应于与标记匹配的功能逻辑噪声前导状态中的识别逻辑检测产生抗噪声。

70. 发明授权

US07065733B2 Method for modifying the behavior of a state machine 失效
标题翻译：修改状态机行为的方法
公开(公告)号：US07065733B2
公开(公告)日：2006-06-20
申请号：US10725712
申请日：2003-12-02
申请人： Kenneth J. Goodnow , Clarence R. Ogilvié , Christ pher B. Reynolds , Jack R. Smith , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Clarence R. Ogilvié , Christ pher B. Reynolds , Jack R. Smith , Sebastian T. Ventrone
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： A method and system for modifying the function of a state machine having a programmable logic device. The method includes the steps of modifying a high-level design of the state machine to obtain a modified high-level design of the state machine with a modified function; generating a programmable logic device netlist from differences in the high-level design and the high-level modified design; and installing the modified function into the state machine by programming the programmable logic device based on the programmable logic device netlist.
摘要翻译：一种用于修改具有可编程逻辑器件的状态机的功能的方法和系统。该方法包括以下步骤：修改状态机的高级设计，以获得具有修改功能的状态机的修改的高级设计; 从高级设计和高级修改设计的差异中产生可编程逻辑器件网表; 并通过基于可编程逻辑器件网表对可编程逻辑器件进行编程，将修改后的功能安装到状态机中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式