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61. 发明授权

US5931924A Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two pseudo-random priority weights 失效
标题翻译：用于控制对共享资源的访问的方法和系统，其中至少一个请求者被同时分配至少两个伪随机优先权重
公开(公告)号：US5931924A
公开(公告)日：1999-08-03
申请号：US839437
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
IPC分类号： G06F15/16 , G06F13/364 , G06F15/177 , G06F13/14
CPC分类号： G06F13/364
摘要： A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is associated with a priority weight that indicates a probability that the associated requester will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requesters. In response to the current priorities of the requesters, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.
摘要翻译：描述了用于控制对数据处理系统中的共享资源的访问的方法和系统。根据该方法，通过共享资源的多个请求者生成对资源的访问的多个请求。每个请求者与优先级权重相关联，该权重指示相关请求者将被分配最高当前优先级的概率。然后分配每个请求者相对于请求者的先前优先级基本随机确定的当前优先级。为响应请求者的当前优先级，授予访问资源的请求。在一个实施例中，与被许可的请求相对应的请求者用信号通知其请求已经被许可，并且与被拒绝的请求相对应的请求者用信号通知其请求未被授予。

62. 发明授权

US5893163A Method and system for allocating data among cache memories within a symmetric multiprocessor data-processing system 失效
标题翻译：用于在对称多处理器数据处理系统内的高速缓冲存储器之间分配数据的方法和系统
公开(公告)号：US5893163A
公开(公告)日：1999-04-06
申请号：US992135
申请日：1997-12-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0811
摘要： A method and system for allocating data among cache memories within a symmetric multiprocessor data-processing system are disclosed. The symmetric multiprocessor data-processing system includes a system memory and multiple processing units, wherein each of the processing units has a cache memory. The system memory is divided into a number of segments, wherein the number of segments is equal to the total number of cache memories. Each of these segments is represented by one of the cache memories such that a cache memory is responsible to cache data from its associated segment within the system memory.
摘要翻译：公开了一种用于在对称多处理器数据处理系统内的高速缓存存储器中分配数据的方法和系统。对称多处理器数据处理系统包括系统存储器和多个处理单元，其中每个处理单元具有高速缓冲存储器。系统存储器被分成多个段，其中段的数量等于高速缓冲存储器的总数。这些段中的每一个由高速缓冲存储器之一表示，使得高速缓冲存储器负责缓存来自系统存储器内的相关段的数据。

63. 发明授权

US5796979A Data processing system having demand based write through cache with enforced ordering 失效
标题翻译：数据处理系统具有基于需求的写入通过缓存执行排序
公开(公告)号：US5796979A
公开(公告)日：1998-08-18
申请号：US730994
申请日：1996-10-16
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F13/12
CPC分类号： G06F12/0866 , G06F12/0815 , G06F12/0835 , G06F2212/303
摘要： A data processing system includes a processor, a system memory, one or more input/output channel controllers (IOCC), and a system bus connecting the processor, the memory and the IOCCs together for communicating instructions, address and data between the various elements of a system. The IOCC includes a paged cache storage having a number of lines wherein each line of the page may be, for example, 32 bytes. Each page in the cache also has several attribute bits for that page including the so called WIM and attribute bits. The W bit is for controlling write through operations; the I bit controls cache inhibit; and the M bit controls memory coherency. Since the IOCC is unaware of these page table attribute bits for the cache lines being DMAed to system memory, IOCC must maintain memory consistency and cache coherency without sacrificing performance. For DMA write data to system memory, new cache attributes called global, cachable and demand based write through are created. Individual writes within a cache line are gathered by the IOCC and only written to system memory when the I/O bus master accesses a different cache line or relinquishes the I/O bus.
摘要翻译：数据处理系统包括处理器，系统存储器，一个或多个输入/输出通道控制器（IOCC）以及将处理器，存储器和IOCC连接在一起的系统总线，用于在各种元件之间传送指令，地址和数据一个系统。 IOCC包括具有多行的分页缓存存储器，其中页面的每行可以是例如32字节。缓存中的每个页面还具有该页面的几个属性位，包括所谓的WIM和属性位。 W位用于控制写操作; I位控制缓存抑制; M位控制存储器一致性。由于IOCC不知道将这些页表属性位用于高速缓存行被DMA映射到系统内存，因此IOCC必须保持内存一致性和高速缓存一致性，而不会牺牲性能。对于将DMA写入数据到系统内存，创建了称为全局，可高速缓存和基于需求的写入的新缓存属性。高速缓存行中的单独写入由IOCC收集，只有当I / O总线主机访问不同的高速缓存行或放弃I / O总线时才写入系统存储器。

64. 发明授权

US06763434B2 Data processing system and method for resolving a conflict between requests to modify a shared cache line 失效
标题翻译：用于解决修改共享缓存行的请求之间的冲突的数据处理系统和方法
公开(公告)号：US06763434B2
公开(公告)日：2004-07-13
申请号：US09752947
申请日：2000-12-30
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Derek Edward Williams
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Disclosed herein are a data processing system and method of operating a data processing system that arbitrate between conflicting requests to modify data cached in a shared state and that protect ownership of the cache line granted during such arbitration until modification of the data is complete. The data processing system includes a plurality of agents coupled to an interconnect that supports pipelined transactions. While data associated with a target address are cached at a first agent among the plurality of agents in a shared state, the first agent issues a transaction on the interconnect. In response to snooping the transaction, a second agent provides a snoop response indicating that the second agent has a pending conflicting request and a coherency decision point provides a snoop response granting the first agent ownership of the data. In response to the snoop responses, the first agent is provided with a combined response representing a collective response to the transaction of all of the agents that grants the first agent ownership of the data. In response to the combined response, the first agent is permitted to modify the data.
摘要翻译：这里公开了一种数据处理系统和方法，该数据处理系统和方法在数据处理系统之间进行仲裁，以便在冲突的请求之间进行仲裁，以修改在共享状态下缓存的数据，并保护在此类仲裁期间授予的高速缓存行的所有权，直到数据修改完成。数据处理系统包括耦合到支持流水线交易的互连的多个代理。虽然与目标地址相关联的数据在共享状态的多个代理之间的第一代理处被高速缓存，但第一代理在互连上发布事务。响应于窥探事务，第二代理提供窥探响应，指示第二代理具有待决冲突请求，并且一致性决策点提供准备数据的第一代理所有权的窥探响应。响应于窥探响应，向第一代理提供组合的响应，其表示对授予数据的第一代理所有权的所有代理的交易的集体响应。响应于组合的响应，允许第一代理修改数据。

65. 发明授权

US06760809B2 Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memory 失效
标题翻译：具有集成在系统存储器内的远程存储器缓存的非均匀存储器访问（NUMA）数据处理系统
公开(公告)号：US06760809B2
公开(公告)日：2004-07-06
申请号：US09885992
申请日：2001-06-21
申请人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0813 , G06F12/0817 , G06F12/0831
摘要： A non-uniform memory access (NUMA) computer system and associated method of operation are disclosed. The NUMA computer system includes at least a remote node and a home node coupled to an interconnect. The remote node contains at least one processing unit coupled to a remote system memory, and the home node contains at least a home system memory. To reduce access latency for data from other nodes, a portion of the remote system memory is allocated as a remote memory cache containing data corresponding to data resident in the home system memory. In one embodiment, access bandwidth to the remote memory cache is increased by distributing the remote memory cache across multiple system memories in the remote node.
摘要翻译：公开了一种非均匀存储器访问（NUMA）计算机系统及其相关操作方法。 NUMA计算机系统至少包括耦合到互连的远程节点和家庭节点。远程节点包含耦合到远程系统存储器的至少一个处理单元，并且家庭节点至少包含家用系统存储器。为了减少来自其他节点的数据的访问延迟，远程系统存储器的一部分被分配为包含对应于驻留在家庭系统存储器中的数据的数据的远程存储器高速缓存。在一个实施例中，通过在远程节点中的多个系统存储器上分发远程存储器高速缓存来增加对远程存储器高速缓存的访问带宽。

66. 发明授权

US06691220B1 Multiprocessor speculation mechanism via a barrier speculation flag 有权
标题翻译：通过屏障投机标志的多处理器推测机制
公开(公告)号：US06691220B1
公开(公告)日：2004-02-10
申请号：US09588608
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F900
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3859
摘要： A method of operation within a processor that permits load instructions following barrier instructions in an instruction sequence to be issued speculatively. The barrier instruction is executed and while the barrier operation is pending, a load request associated with the load instruction is speculatively issued. A speculation flag is set to indicate the load instruction was speculatively issued. The flag is reset when an acknowledgment of the barrier operation is received. Data that is returned before the acknowledgment is received is temporarily held, and the data is forwarded to the register and/or execution unit of the processor only after the acknowledgment is received. If a snoop invalidate is detected for the speculatively issued load request before the barrier operation completes, the data is discarded and the load request is re-issued.
摘要翻译：一种处理器内的操作方法，其允许按照指令序列中的障碍指令之后的加载指令进行推测。屏障指令被执行，并且当屏障操作正在等待时，推测地发出与加载指令相关联的加载请求。设置了一个猜测标志来指示加载指令被推测发出。当接收到屏障操作的确认时，该标志被复位。在接收到确认之前返回的数据被暂时保留，并且仅在接收到确认之后将数据转发到处理器的寄存器和/或执行单元。如果在屏障操作完成之前，对于推测发出的负载请求检测到窥探无效，则丢弃数据并重新发出加载请求。

67. 发明授权

US06625660B1 Multiprocessor speculation mechanism for efficiently managing multiple barrier operations 有权
标题翻译：用于有效管理多个屏障操作的多处理器推测机制
公开(公告)号：US06625660B1
公开(公告)日：2003-09-23
申请号：US09588605
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F1516
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3867
摘要： Disclosed is a method of operation within a processor that permits load instructions to be issued speculatively. An instruction sequence is received that includes multiple barrier instructions and a load instruction that follows the barrier instructions in the instruction sequence. In response to the multiple barrier instructions, barrier operations are issued on an interconnect coupled to the processor. Also, while the barrier operations are pending, a load request associated with the load instruction is speculatively issued. When the load request is issued, a flag is set to indicate that it was speculatively issued. The flag is reset when acknowledgments of all the barrier operations are received. Data that is returned before the acknowledgments are received is temporarily held and forwarded to the register and/or execution unit of the processor only after the acknowledgments are received. If a snoop invalidate is detected for the speculatively issued load request before completion of the barrier operations, the data is discarded and the load request is re-issued.
摘要翻译：公开了一种在处理器内操作的方法，其允许以推测方式发布加载指令。接收包括多个屏障指令和跟随指令序列中的屏障指令的加载指令的指令序列。响应于多个屏障指令，在耦合到处理器的互连上发出屏障操作。此外，当屏障操作正在等待时，推测性地发出与加载指令相关联的加载请求。当发出加载请求时，会设置一个标志来指示它被推测发出。当接收到所有屏障操作的确认时，该标志被复位。在接收到确认之前返回的数据被暂时保存，并且在接收到确认之后被转发到处理器的寄存器和/或执行单元。如果在完成屏障操作之前，对于推测发出的加载请求检测到窥探无效，则丢弃数据并重新发出加载请求。

68. 发明授权

US06615321B2 Mechanism for collapsing store misses in an SMP computer system 有权
公开(公告)号：US06615321B2
公开(公告)日：2003-09-02
申请号：US09782581
申请日：2001-02-12
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/0855 , G06F12/0831
摘要： A method of handling a write operation in a multiprocessor computer system wherein each processing unit has a respective cache, by determining that a new value for a store instruction is the same as a current value already contained in the memory hierarchy, and discarding the store instruction without issuing any associated cache operation in response to this determination. When a store hit occurs, the current value is retrieved from the local cache. When a store miss occurs, the current value is retrieved from a remote cache by issuing a read request. The comparison may be performed using a portion of the cache line which is less than a granule size of the cache line. A store gathering queue can be use to collect pending store instructions that are directed to different portions of the same cache line.

69. 发明授权

US06615320B2 Store collapsing mechanism for SMP computer system 有权
公开(公告)号：US06615320B2
公开(公告)日：2003-09-02
申请号：US09782580
申请日：2001-02-12
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/0815 , G06F12/0831
摘要： A method of handling a write operation in a multiprocessor computer system wherein each processing unit has a respective cache, by determining that a new value for a store instruction is the same as a current value already contained in the memory hierarchy, and discarding the store instruction without issuing any associated cache operation in response to this determination. When a store hit occurs, the current value is retrieved from the local cache. When a store miss occurs, the current value is retrieved from a remote cache by issuing a read request. The comparison may be performed using a portion of the cache line which is less than a granule size of the cache line. A store gathering queue can be use to collect pending store instructions that are directed to different portions of the same cache line.

70. 发明授权

US06587924B2 Scarfing within a hierarchical memory architecture 有权
标题翻译：在分层内存架构中进行扫描
公开(公告)号：US06587924B2
公开(公告)日：2003-07-01
申请号：US09903727
申请日：2001-07-12
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , Y10S707/99931
摘要： A method and system for scarfing data during a data access transaction within a hierarchical data storage system. A data access request is delivered from a source device to a plurality of data storage devices. The access request includes a target address and a source path tag, wherein the source path tag includes a device identification tag that uniquely identifies a data storage device within a given level of the system traversed by the access request. A device identification tag that uniquely identifies the third party transactor within a given memory level is appended to the source path tag such that the third party transactor can scarf returning data without reserving a scarf queue entry.
摘要翻译：一种用于在分层数据存储系统内的数据访问事务期间对数据进行分页的方法和系统。数据访问请求从源设备传送到多个数据存储设备。访问请求包括目标地址和源路径标签，其中源路径标签包括唯一地标识由访问请求遍历的系统的给定级别内的数据存储设备的设备标识标签。唯一地标识给定存储器级别内的第三方交易者的设备识别标签被附加到源路径标签，使得第三方交易者可以围绕返回数据而不预留围巾队列条目。

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