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1. 发明授权

US06763434B2 Data processing system and method for resolving a conflict between requests to modify a shared cache line 失效
标题翻译：用于解决修改共享缓存行的请求之间的冲突的数据处理系统和方法
公开(公告)号：US06763434B2
公开(公告)日：2004-07-13
申请号：US09752947
申请日：2000-12-30
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Derek Edward Williams
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Disclosed herein are a data processing system and method of operating a data processing system that arbitrate between conflicting requests to modify data cached in a shared state and that protect ownership of the cache line granted during such arbitration until modification of the data is complete. The data processing system includes a plurality of agents coupled to an interconnect that supports pipelined transactions. While data associated with a target address are cached at a first agent among the plurality of agents in a shared state, the first agent issues a transaction on the interconnect. In response to snooping the transaction, a second agent provides a snoop response indicating that the second agent has a pending conflicting request and a coherency decision point provides a snoop response granting the first agent ownership of the data. In response to the snoop responses, the first agent is provided with a combined response representing a collective response to the transaction of all of the agents that grants the first agent ownership of the data. In response to the combined response, the first agent is permitted to modify the data.
摘要翻译：这里公开了一种数据处理系统和方法，该数据处理系统和方法在数据处理系统之间进行仲裁，以便在冲突的请求之间进行仲裁，以修改在共享状态下缓存的数据，并保护在此类仲裁期间授予的高速缓存行的所有权，直到数据修改完成。数据处理系统包括耦合到支持流水线交易的互连的多个代理。虽然与目标地址相关联的数据在共享状态的多个代理之间的第一代理处被高速缓存，但第一代理在互连上发布事务。响应于窥探事务，第二代理提供窥探响应，指示第二代理具有待决冲突请求，并且一致性决策点提供准备数据的第一代理所有权的窥探响应。响应于窥探响应，向第一代理提供组合的响应，其表示对授予数据的第一代理所有权的所有代理的交易的集体响应。响应于组合的响应，允许第一代理修改数据。

2. 发明授权

US06691220B1 Multiprocessor speculation mechanism via a barrier speculation flag 有权
标题翻译：通过屏障投机标志的多处理器推测机制
公开(公告)号：US06691220B1
公开(公告)日：2004-02-10
申请号：US09588608
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F900
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3859
摘要： A method of operation within a processor that permits load instructions following barrier instructions in an instruction sequence to be issued speculatively. The barrier instruction is executed and while the barrier operation is pending, a load request associated with the load instruction is speculatively issued. A speculation flag is set to indicate the load instruction was speculatively issued. The flag is reset when an acknowledgment of the barrier operation is received. Data that is returned before the acknowledgment is received is temporarily held, and the data is forwarded to the register and/or execution unit of the processor only after the acknowledgment is received. If a snoop invalidate is detected for the speculatively issued load request before the barrier operation completes, the data is discarded and the load request is re-issued.
摘要翻译：一种处理器内的操作方法，其允许按照指令序列中的障碍指令之后的加载指令进行推测。屏障指令被执行，并且当屏障操作正在等待时，推测地发出与加载指令相关联的加载请求。设置了一个猜测标志来指示加载指令被推测发出。当接收到屏障操作的确认时，该标志被复位。在接收到确认之前返回的数据被暂时保留，并且仅在接收到确认之后将数据转发到处理器的寄存器和/或执行单元。如果在屏障操作完成之前，对于推测发出的负载请求检测到窥探无效，则丢弃数据并重新发出加载请求。

3. 发明授权

US06625660B1 Multiprocessor speculation mechanism for efficiently managing multiple barrier operations 有权
标题翻译：用于有效管理多个屏障操作的多处理器推测机制
公开(公告)号：US06625660B1
公开(公告)日：2003-09-23
申请号：US09588605
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F1516
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3867
摘要： Disclosed is a method of operation within a processor that permits load instructions to be issued speculatively. An instruction sequence is received that includes multiple barrier instructions and a load instruction that follows the barrier instructions in the instruction sequence. In response to the multiple barrier instructions, barrier operations are issued on an interconnect coupled to the processor. Also, while the barrier operations are pending, a load request associated with the load instruction is speculatively issued. When the load request is issued, a flag is set to indicate that it was speculatively issued. The flag is reset when acknowledgments of all the barrier operations are received. Data that is returned before the acknowledgments are received is temporarily held and forwarded to the register and/or execution unit of the processor only after the acknowledgments are received. If a snoop invalidate is detected for the speculatively issued load request before completion of the barrier operations, the data is discarded and the load request is re-issued.
摘要翻译：公开了一种在处理器内操作的方法，其允许以推测方式发布加载指令。接收包括多个屏障指令和跟随指令序列中的屏障指令的加载指令的指令序列。响应于多个屏障指令，在耦合到处理器的互连上发出屏障操作。此外，当屏障操作正在等待时，推测性地发出与加载指令相关联的加载请求。当发出加载请求时，会设置一个标志来指示它被推测发出。当接收到所有屏障操作的确认时，该标志被复位。在接收到确认之前返回的数据被暂时保存，并且在接收到确认之后被转发到处理器的寄存器和/或执行单元。如果在完成屏障操作之前，对于推测发出的加载请求检测到窥探无效，则丢弃数据并重新发出加载请求。

4. 发明授权

US06963967B1 System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture 失效
标题翻译：系统和方法能够使稳定的存储优势与稳定的存储架构相结合
公开(公告)号：US06963967B1
公开(公告)日：2005-11-08
申请号：US09588508
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In response to receipt of the memory access instruction a memory access request and a barrier operation are created. The barrier operation is placed on an interconnect after the memory access request is issued to a memory system. After the barrier operation has completed, the memory access request is completed in program order. When the memory access request is a load request, the load request is speculatively issued if a barrier operation is pending. Data returned by the speculatively issued load request is only returned to a register or execution unit of the processor when an acknowledgment is received for the barrier operation.
摘要翻译：公开了一种在数据处理系统中处理指令的方法。包括存储器访问指令的指令序列以处理器的顺序被接收。响应于接收到存储器访问指令，创建存储器访问请求和屏障操作。在将存储器访问请求发布到存储器系统之后，屏障操作被放置在互连上。屏障操作完成后，按程序顺序完成内存访问请求。当存储器访问请求是加载请求时，如果屏障操作正在等待，则推测性地发出加载请求。当接收到用于屏障操作的确认时，由推测发出的加载请求返回的数据仅返回到处理器的寄存器或执行单元。

5. 发明授权

US06609192B1 System and method for asynchronously overlapping storage barrier operations with old and new storage operations 有权
标题翻译：使用旧的和新的存储操作异步重叠存储屏障操作的系统和方法
公开(公告)号：US06609192B1
公开(公告)日：2003-08-19
申请号：US09588607
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F9312
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3842
摘要： Disclosed is a multiprocessor data processing system that executes loads transactions out of order with respect to a barrier operation. The data processing system includes a memory and a plurality of processors coupled to an interconnect. At least one of the processors includes an instruction sequencing unit for fetching an instruction sequence in program order for execution. The instruction sequence includes a first and a second load instruction and a barrier instruction, which is between the first and second load instructions in the instruction sequence. Also included in the processor is a load/store unit (LSU), which has a load request queue (LRQ) that temporarily buffers load requests associated with the first and second load instructions. The LRQ is coupled to a load request arbitration unit, which selects an order of issuing the load requests from the LRQ. Then a controller issues a load request associated with the second load instruction to memory before completion of a barrier operation associated with the barrier instruction. Alternatively, load requests are issued out-of-order with respect to the program order before or after the barrier instruction. The load request arbitration unit selects the request associated with the second load instruction before a request associated with the first load instruction, and the controller issues the request associated with the second load instruction before the request associated with the first load instruction and before issuing the barrier operation.
摘要翻译：公开了一种多处理器数据处理系统，其针对屏障操作执行无序的负载事务。数据处理系统包括存储器和耦合到互连的多个处理器。至少一个处理器包括用于以程序顺序取出指令序列以执行的指令排序单元。指令序列包括在指令序列中的第一和第二加载指令之间的第一和第二加载指令和障碍指令。还包括在处理器中的是装载/存储单元（LSU），其具有临时缓冲与第一和第二加载指令相关联的加载请求的加载请求队列（LRQ）。 LRQ耦合到负载请求仲裁单元，该单元从LRQ中选择发出负载请求的顺序。然后，在与障碍指令相关联的屏障操作完成之前，控制器向存储器发出与第二加载指令相关联的加载请求。或者，负载请求在屏障指令之前或之后相对于程序顺序发出无序。负载请求仲裁单元在与第一加载指令相关联的请求之前选择与第二加载指令相关联的请求，并且控制器在与第一加载指令相关联的请求之前发布与第二加载指令相关联的请求，并且在发布屏障之前操作。

6. 发明授权

US06748518B1 Multi-level multiprocessor speculation mechanism 有权
标题翻译：多级多处理器推测机制
公开(公告)号：US06748518B1
公开(公告)日：2004-06-08
申请号：US09588483
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F930
CPC分类号： G06F9/3834 , G06F9/30087 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3859
摘要： Disclosed is a processor, which reduces issuing of unnecessary barrier operations during instruction processing. The processor comprises an instruction sequencing unit and a load store unit (LSU) that issues a group of memory access requests that precede a barrier instruction in an instruction sequence. The processor also includes a controller, which in response to a determination that all of the memory access requests hit in a cache affiliated with the processor, withholds issuing on an interconnect a barrier operation associated with the barrier instruction. The controller further directs the load store unit to ignore the barrier instruction and complete processing of a next group of memory access requests following the barrier instruction in the instruction sequence without receiving an acknowledgment.
摘要翻译：公开了一种处理器，其减少在指令处理期间发出不必要的屏障操作。处理器包括指令排序单元和负载存储单元（LSU），其发出在指令序列中的屏障指令之前的一组存储器访问请求。处理器还包括控制器，其响应于确定在处理器附属的高速缓存中的所有存储器访问请求，在互连上保留与屏障指令相关联的屏障操作。控制器进一步引导加载存储单元忽略屏障指令，并且在指令序列中的屏障指令之后的下一组存储器访问请求完成处理而不接收到确认。

7. 发明授权

US06606702B1 Multiprocessor speculation mechanism with imprecise recycling of storage operations 有权
标题翻译：多处理器推测机制，存储操作不正确的回收
公开(公告)号：US06606702B1
公开(公告)日：2003-08-12
申请号：US09588606
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F9312
CPC分类号： G06F9/3842 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/52 , G06F9/522
摘要： Disclosed is a method of operating a processor, by which a speculatively issued load request, which fetches incorrect data, is recycled. An instruction sequence, which includes a barrier instruction and a load instruction that follows the barrier instruction in program order, is received for execution. In response to the barrier instruction, a barrier operation is issued on an interconnect. Following, in response to the load instruction and while the barrier operation is pending, a load request is issued to memory. When a pre-determined type of invalidate, which is affiliated with the load request, is received before the receipt of an acknowledgment for the barrier operation, data that is returned by memory in response to the load request is discarded and the load request is re-issued. The pre-determined type of invalidate includes, for example, a snoop invalidate.
摘要翻译：公开了一种操作处理器的方法，通过该方法，回收了推测性发出的载入请求，其提取不正确的数据。接收指令序列，其中包括按程序顺序跟随障碍指令的障碍指令和加载指令，以执行。响应于屏障指令，在互连上发出屏障操作。接下来，响应于加载指令，并且当屏障操作正在等待时，向存储器发出加载请求。当在接收到屏障操作的确认之前接收到与加载请求相关联的预定类型的无效时，丢弃由存储器响应于加载请求而返回的数据，并且重新加载请求 -发行。预定类型的无效包括例如窥探无效。

8. 发明授权

US06880073B2 Speculative execution of instructions and processes before completion of preceding barrier operations 失效
标题翻译：完成前面的障碍操作之前，对指令和过程的推测执行
公开(公告)号：US06880073B2
公开(公告)日：2005-04-12
申请号：US09753053
申请日：2000-12-28
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Derek Edward Williams
IPC分类号： G06F9/30 , G06F9/38 , G06F9/00
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842
摘要： Described is a data processing system and processor that provides full multiprocessor speculation by which all instructions subsequent to barrier operations in a instruction sequence are speculatively executed before the barrier operation completes on the system bus. The processor comprises a load/store unit (LSU) with a barrier operation (BOP) controller that permits load instructions subsequent to syncs in an instruction sequence to be speculatively issued prior to the return of the sync acknowledgment. Data returned is immediately forwarded to the processor's execution units. The returned data and results of subsequent operations are held temporarily in rename registers. A multiprocessor speculation flag is set in the corresponding rename registers to indicate that the value is “barrier” speculative. When a barrier acknowledge is received by the BOP controller, the flag(s) of the corresponding rename register(s) are reset.
摘要翻译：描述了提供完整的多处理器推测的数据处理系统和处理器，在系统总线上的屏障操作完成之前，推测性地执行指令序列中的屏障操作之后的所有指令。处理器包括具有屏障操作（BOP）控制器的加载/存储单元（LSU），其允许在指令序列中的同步之后的加载指令在返回同步确认之前被推测地发出。返回的数据立即转发到处理器的执行单元。返回的数据和后续操作的结果暂时保存在重命名寄存器中。在相应的重命名寄存器中设置多处理器推测标志，以指示该值为“屏障”推测。当BOP控制器接收到屏障确认时，相应的重命名寄存器的标志被重置。

9. 发明授权

US06728873B1 System and method for providing multiprocessor speculation within a speculative branch path 失效
标题翻译：在推测性分支路径中提供多处理器推测的系统和方法
公开(公告)号：US06728873B1
公开(公告)日：2004-04-27
申请号：US09588507
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F9312
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3842
摘要： Disclosed is a method of operation within a processor, that enhances speculative branch processing. A speculative execution path contains an instruction sequence that includes a barrier instruction followed by a load instruction. While a barrier operation associated with the barrier instruction is pending, a load request associated with the load instruction is speculatively issued to memory. A flag is set for the load request when it is speculatively issued and reset when an acknowledgment is received for the barrier operation. Data which is returned by the speculatively issued load request is temporarily held and forwarded to a register or execution unit of the data processing system after the acknowledgment is received. All process results, including data returned by the speculatively issued load instructions are discarded when the speculative execution path is determined to be incorrect.
摘要翻译：公开了一种处理器内的操作方法，其增强了推测性分支处理。推测执行路径包含指令序列，其中包含跟随加载指令的障碍指令。当与障碍指令相关联的障碍操作正在等待时，与加载指令相关联的加载请求被推测地发布到存储器。当推测性地发出加载请求时设置标志，并且当接收到用于屏障操作的确认时，重置该标志。在接收到确认之后，由推测发出的加载请求返回的数据被暂时保存并转发到数据处理系统的寄存器或执行单元。当推测性执行路径被确定为不正确时，所有处理结果（包括由推测发出的加载指令返回的数据）被丢弃。

10. 发明授权

US06725340B1 Mechanism for folding storage barrier operations in a multiprocessor system 失效
标题翻译：在多处理器系统中折叠存储屏障操作的机制
公开(公告)号：US06725340B1
公开(公告)日：2004-04-20
申请号：US09588509
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F9312
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3859
摘要： Disclosed is a processor that reduces barrier operations during instruction processing. An instruction sequence includes a first barrier instruction and a second barrier instruction with a store instruction in between the first and second barrier instructions. A store request associated with the store instruction is issued prior to a barrier operation associated with the first barrier instruction. A determination is made of when the store request completes before the first barrier instruction has issued. In response, only a single barrier operation is issued for both the first and second barrier instructions. The single barrier operation is issued after the store request has been issued and at the time the second barrier operation is scheduled to be issued.
摘要翻译：公开了一种在指令处理期间减少屏障操作的处理器。指令序列包括在第一和第二屏障指令之间具有存储指令的第一屏障指令和第二屏障指令。在与第一屏障指令相关联的屏障操作之前发出与存储指令相关联的存储请求。确定存储请求何时在第一个屏障指令发出之前完成。作为响应，仅为第一和第二屏障指令发出单个屏障操作。单个屏障操作在存储请求已经被发出之后并且在第二屏障操作被安排发布的时候发出。

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