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61. 发明授权

US07603487B2 Hardware configurable hub interface unit 有权
标题翻译：硬件可配置的集线器接口单元
公开(公告)号：US07603487B2
公开(公告)日：2009-10-13
申请号：US11128680
申请日：2005-05-13
申请人： Shoban Srikrishna Jagathesan , Sanjive Agarwala , Raguram Damodaran
发明人： Shoban Srikrishna Jagathesan , Sanjive Agarwala , Raguram Damodaran
IPC分类号： G06F3/00 , G06F13/00 , G06F13/12
CPC分类号： G06F13/28 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application units. The configurable HIU provides a single generic superset HIU that can be configured for specific more specialized applications during implementation as part of design synthesis. Configuration allows the super-set configurable HIU to be crafted into any one of several possible special purpose HIUs. This configuration is performed during the design phase and is not applied in field applications. Optimization aimed at eliminating functional blocks not needed in a specific design and simplifying and modifying other functional blocks allows for the efficient configuring of these other types of HIUs. Configuration of HIUs for specific needs can result in significant savings in silicon area and in power consumption.
摘要翻译：具有集线器和端口的数据传输装置包括在端口和相应的外部应用单元之间的设计可配置的集线器接口单元（HIU）。可配置的HIU提供单个通用超集HIU，可以在实现过程中为特定的更专门的应用程序配置，这是设计综合的一部分。配置允许将超级可配置HIU制作成几个可能的专用HIU中的任何一个。此配置在设计阶段执行，不适用于现场应用。旨在消除特定设计中不需要的功能块的优化，并简化和修改其他功能块允许有效配置这些其他类型的HIU。为特定需要配置HIU可以显着节省硅面积和功耗。

62. 发明授权

US07444573B2 VLCT programmation/read protocol 有权
标题翻译： VLCT程序设计/读取协议
公开(公告)号：US07444573B2
公开(公告)日：2008-10-28
申请号：US11422751
申请日：2006-06-07
申请人： Raguram Damodaran , Ananthakrishnan Ramamurti , Ravi Lakshmanan
发明人： Raguram Damodaran , Ananthakrishnan Ramamurti , Ravi Lakshmanan
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G06F11/27
摘要： An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit receives a command, an address and a data transfer count. The address specifies the initial data register address. The data transfer count corresponds to the amount of data transferred and the number of cycle in the data access phase. The data access phase begins by accessing the data register corresponding to the address from the command phase. During subsequent cycles of the data access phase, the external tester accesses sequential data registers. The programmable built-in self test unit includes a pointer register and an adder to update the address each cycle of the data phase.
摘要翻译：具有内置自检功能的集成电路可通过外部测试仪将内部数据寄存器写入或读取。在命令阶段，可编程内置自检单元接收命令，地址和数据传输计数。地址指定初始数据寄存器地址。数据传输计数对应于传输的数据量和数据访问阶段的周期数。数据访问阶段从命令阶段访问对应于地址的数据寄存器开始。在数据访问阶段的后续周期期间，外部测试人员访问顺序数据寄存器。可编程内置自检单元包括指针寄存器和加法器，用于在数据相位的每个周期更新地址。

63. 发明申请

US20080068239A1 Entry/Exit Control To/From a Low Power State in a Complex Multi Level Memory System 有权
标题翻译：在复杂的多级存储器系统中进入/退出控制到低功耗状态
公开(公告)号：US20080068239A1
公开(公告)日：2008-03-20
申请号：US11855602
申请日：2007-09-14
申请人： Timothy David Anderson , Lewis Nardini , Jose Luis Flores , Abhijeet Chachad , Raguram Damodaran , Joseph R.M. Zbiciak , Gary Swoboda
发明人： Timothy David Anderson , Lewis Nardini , Jose Luis Flores , Abhijeet Chachad , Raguram Damodaran , Joseph R.M. Zbiciak , Gary Swoboda
IPC分类号： H03M1/00
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.
摘要翻译：嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。

64. 发明授权

US07325178B2 Programmable built in self test of memory 有权
标题翻译：可编程内置自检内存
公开(公告)号：US07325178B2
公开(公告)日：2008-01-29
申请号：US11003206
申请日：2004-12-03
申请人： Raguram Damodaran , Timothy D. Anderson , Sanjive Agarwala , Joel J. Graber
发明人： Raguram Damodaran , Timothy D. Anderson , Sanjive Agarwala , Joel J. Graber
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/16
摘要： The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.
摘要翻译：内存测试的pBIST解决方案是一个平衡的面向硬件的软件解决方案。 pBIST硬件提供对允许背靠背访问的流水线逻辑中的所有存储器和其他这样的逻辑（例如寄存器文件）的访问。该方法然后让用户通过类似CPU的逻辑访问该逻辑，其中程序员可以对任何算法进行编码，以定位所需的任何内存测试技术。由于芯片内部的硬件速度被使用，因此可以提供全部设备速度功能。类似CPU的硬件可以进行编程，并且可以在磁带输出之后开发和执行算法，同时在芯片形式的器件上进行测试。

65. 发明授权

US07240277B2 Memory error detection reporting 有权
标题翻译：内存错误检测报告
公开(公告)号：US07240277B2
公开(公告)日：2007-07-03
申请号：US10950797
申请日：2004-09-27
申请人： Timothy D. Anderson , David Q. Bell , Abhijeet A. Chachad , Peter Dent , Raguram Damodaran
发明人： Timothy D. Anderson , David Q. Bell , Abhijeet A. Chachad , Peter Dent , Raguram Damodaran
IPC分类号： G06F11/10 , G06F12/04
CPC分类号： G06F11/1032
摘要： A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.
摘要翻译：存储器系统或数字信号处理器（DSP）包括其二级（L2）存储器控制器中的单位错误检测硬件，以减轻软错误的影响。错误检测硬件检测由中央处理单元取出并向中央处理单元发出信号的错误数据。仅对整个存储器线路访问生成和检查奇偶校验。这种技术对缓存特别有用。中央处理单元可以根据生成错误的特定位置查询存储器控制器，并根据受影响的数据类型决定下一个操作过程。

66. 发明申请

US20070033472A1 VLCT Programmation/Read Protocol 有权
标题翻译： VLCT程序设计/读取协议
公开(公告)号：US20070033472A1
公开(公告)日：2007-02-08
申请号：US11422751
申请日：2006-06-07
申请人： Raguram Damodaran , Ananthakrishnan Ramamurti , Ravi Lakshmanan
发明人： Raguram Damodaran , Ananthakrishnan Ramamurti , Ravi Lakshmanan
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G06F11/27
摘要： An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit receives a command, an address and a data transfer count. The address specifies the initial data register address. The data transfer count corresponds to the amount of data transferred and the number of cycle in the data access phase. The data access phase begins by accessing the data register corresponding to the address from the command phase. During subsequent cycles of the data access phase, the external tester accesses sequential data registers. The programmable built-in self test unit includes a pointer register and an adder to update the address each cycle of the data phase.
摘要翻译：具有内置自检功能的集成电路可通过外部测试仪将内部数据寄存器写入或读取。在命令阶段，可编程内置自检单元接收命令，地址和数据传输计数。地址指定初始数据寄存器地址。数据传输计数对应于传输的数据量和数据访问阶段的周期数。数据访问阶段从命令阶段访问对应于地址的数据寄存器开始。在数据访问阶段的后续周期期间，外部测试人员访问顺序数据寄存器。可编程内置自检单元包括指针寄存器和加法器，用于在数据相位的每个周期更新地址。

67. 发明申请

US20060282719A1 Unique Addressable Memory Data Path 审中-公开
标题翻译：唯一可寻址内存数据路径
公开(公告)号：US20060282719A1
公开(公告)日：2006-12-14
申请号：US11383324
申请日：2006-05-15
申请人： Raguram Damodaran
发明人： Raguram Damodaran
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： Instead of using point to point connections between the memory and the memory test controller, a unique address is assigned to each memory element. The memory elements and the single memory test controller are interconnected by a hierarchal datapath both for the memory addresses and for the resultant data being returned to the memory test controller.
摘要翻译：代替在存储器和存储器测试控制器之间使用点对点连接，将唯一的地址分配给每个存储器元件。存储器元件和单个存储器测试控制器通过用于存储器地址的分层数据路径和返回到存储器测试控制器的结果数据互连。

68. 发明授权

US06594713B1 Hub interface unit and application unit interfaces for expanded direct memory access processor 有权
标题翻译： Hub接口单元和应用单元接口，用于扩展的直接存储器访问处理器
公开(公告)号：US06594713B1
公开(公告)日：2003-07-15
申请号：US09637492
申请日：2000-08-11
申请人： Charles Fuoco , David A. Comisky , Sanjive Agarwala , Raguram Damodaran
发明人： Charles Fuoco , David A. Comisky , Sanjive Agarwala , Raguram Damodaran
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： An expanded direct memory access processor has ports which may be divided into two sections. The first is an application specific design referred to as the application unit, or application unit. Between the application unit and the expanded direct memory access processor hub is a second module, known as the hub interface unit hub interface unit which serves several functions. It provides buffering for read and write data, it prioritizes read and write commands from the source and destination pipelines such that the port sees a single interface with both access types consolidated and finally, it acts to decouple the port interface clock domain from the core processor clock domain through synchronization.
摘要翻译：扩展的直接存储器存取处理器具有可分为两部分的端口。第一种是被称为应用单元或应用单元的应用特定设计。在应用单元和扩展的直接存储器访问处理器集线器之间是第二模块，称为集线器接口单元集线器接口单元，其用于多个功能。它为读取和写入数据提供缓冲，它优先考虑来自源和目标管道的读取和写入命令，使得端口看到具有两个访问类型的单个接口合并，最后，它用于将端口接口时钟域与核心处理器时钟域通过同步。

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