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1. 发明授权

US06985982B2 Active ports in a transfer controller with hub and ports 有权
公开(公告)号：US06985982B2
公开(公告)日：2006-01-10
申请号：US10003856
申请日：2001-10-24
申请人： Sanjive Agarwala , David A. Comisky , Charles Fuoco , Raguram Damodaran
发明人： Sanjive Agarwala , David A. Comisky , Charles Fuoco , Raguram Damodaran
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F13/28
摘要： In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.

2. 发明授权

US06594713B1 Hub interface unit and application unit interfaces for expanded direct memory access processor 有权
标题翻译： Hub接口单元和应用单元接口，用于扩展的直接存储器访问处理器
公开(公告)号：US06594713B1
公开(公告)日：2003-07-15
申请号：US09637492
申请日：2000-08-11
申请人： Charles Fuoco , David A. Comisky , Sanjive Agarwala , Raguram Damodaran
发明人： Charles Fuoco , David A. Comisky , Sanjive Agarwala , Raguram Damodaran
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： An expanded direct memory access processor has ports which may be divided into two sections. The first is an application specific design referred to as the application unit, or application unit. Between the application unit and the expanded direct memory access processor hub is a second module, known as the hub interface unit hub interface unit which serves several functions. It provides buffering for read and write data, it prioritizes read and write commands from the source and destination pipelines such that the port sees a single interface with both access types consolidated and finally, it acts to decouple the port interface clock domain from the core processor clock domain through synchronization.
摘要翻译：扩展的直接存储器存取处理器具有可分为两部分的端口。第一种是被称为应用单元或应用单元的应用特定设计。在应用单元和扩展的直接存储器访问处理器集线器之间是第二模块，称为集线器接口单元集线器接口单元，其用于多个功能。它为读取和写入数据提供缓冲，它优先考虑来自源和目标管道的读取和写入命令，使得端口看到具有两个访问类型的单个接口合并，最后，它用于将端口接口时钟域与核心处理器时钟域通过同步。

3. 发明授权

US08904115B2 Cache with multiple access pipelines 有权
标题翻译：具有多路访问管道的缓存
公开(公告)号：US08904115B2
公开(公告)日：2014-12-02
申请号：US13212895
申请日：2011-08-18
申请人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
发明人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
IPC分类号： G06F12/00 , G06F7/483 , G06F12/02 , G06F1/32 , G06F9/30 , H03M13/35 , H03M13/29 , G06F11/10 , H03K19/00 , H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.
摘要翻译：并行流水线用于访问共享内存。通过处理器通过第一管线访问共享存储器以从共享存储器访问缓存的数据。通过存储器访问单元通过第二管线访问共享存储器以访问共享存储器。维持第一组标签以供第一管线使用以控制对高速缓冲存储器的访问，而第二组标签被维护供第二管道用于访问共享存储器。在每个流水线检查其相应的一组标签之后，执行仲裁以访问第一流水线中的事务请求的高速缓冲存储器和第二流水线中的事务请求。

4. 发明申请

US20050172180A1 Programmable built in self test of memory 有权
标题翻译：可编程内置自检内存
公开(公告)号：US20050172180A1
公开(公告)日：2005-08-04
申请号：US11003206
申请日：2004-12-03
申请人： Raguram Damodaran , Timothy Anderson , Sanjive Agarwala , Joel Graber
发明人： Raguram Damodaran , Timothy Anderson , Sanjive Agarwala , Joel Graber
IPC分类号： G11C29/00 , G11C29/16
CPC分类号： G11C29/16
摘要： The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.
摘要翻译：内存测试的pBIST解决方案是一个平衡的面向硬件的软件解决方案。 pBIST硬件提供对允许背靠背访问的流水线逻辑中的所有存储器和其他这样的逻辑（例如寄存器文件）的访问。该方法然后让用户通过类似CPU的逻辑访问该逻辑，其中程序员可以对任何算法进行编码，以定位所需的任何内存测试技术。由于芯片内部的硬件速度被使用，因此可以提供全部设备速度功能。类似CPU的硬件可以进行编程，并且可以在磁带输出之后开发和执行算法，同时在芯片形式的器件上进行测试。

5. 发明申请

US20060259569A1 Hardware configurable hub interface unit 有权
公开(公告)号：US20060259569A1
公开(公告)日：2006-11-16
申请号：US11128680
申请日：2005-05-13
申请人： Shoban Jagathesan , Sanjive Agarwala , Raguram Damodaran
发明人： Shoban Jagathesan , Sanjive Agarwala , Raguram Damodaran
IPC分类号： G06F15/167
CPC分类号： G06F13/28 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application units. The configurable HIU provides a single generic superset HIU that can be configured for specific more specialized applications during implementation as part of design synthesis. Configuration allows the super-set configurable HIU to be crafted into any one of several possible special purpose HIUs. This configuration is performed during the design phase and is not applied in field applications. Optimization aimed at eliminating functional blocks not needed in a specific design and simplifying and modifying other functional blocks allows for the efficient configuring of these other types of HIUs. Configuration of HIUs for specific needs can result in significant savings in silicon area and in power consumption.

6. 发明申请

US20120079204A1 Cache with Multiple Access Pipelines 有权
标题翻译：具有多路访问管道的缓存
公开(公告)号：US20120079204A1
公开(公告)日：2012-03-29
申请号：US13212895
申请日：2011-08-18
申请人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
发明人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.
摘要翻译：并行流水线用于访问共享内存。通过处理器通过第一管线访问共享存储器以从共享存储器访问缓存的数据。通过存储器访问单元通过第二管线访问共享存储器以访问共享存储器。维持第一组标签以供第一管线使用以控制对高速缓冲存储器的访问，而第二组标签被维护供第二管道用于访问共享存储器。在每个流水线检查其相应的一组标签之后，执行仲裁以访问第一流水线中的事务请求的高速缓冲存储器和第二流水线中的事务请求。

7. 发明授权

US07603487B2 Hardware configurable hub interface unit 有权
标题翻译：硬件可配置的集线器接口单元
公开(公告)号：US07603487B2
公开(公告)日：2009-10-13
申请号：US11128680
申请日：2005-05-13
申请人： Shoban Srikrishna Jagathesan , Sanjive Agarwala , Raguram Damodaran
发明人： Shoban Srikrishna Jagathesan , Sanjive Agarwala , Raguram Damodaran
IPC分类号： G06F3/00 , G06F13/00 , G06F13/12
CPC分类号： G06F13/28 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application units. The configurable HIU provides a single generic superset HIU that can be configured for specific more specialized applications during implementation as part of design synthesis. Configuration allows the super-set configurable HIU to be crafted into any one of several possible special purpose HIUs. This configuration is performed during the design phase and is not applied in field applications. Optimization aimed at eliminating functional blocks not needed in a specific design and simplifying and modifying other functional blocks allows for the efficient configuring of these other types of HIUs. Configuration of HIUs for specific needs can result in significant savings in silicon area and in power consumption.
摘要翻译：具有集线器和端口的数据传输装置包括在端口和相应的外部应用单元之间的设计可配置的集线器接口单元（HIU）。可配置的HIU提供单个通用超集HIU，可以在实现过程中为特定的更专门的应用程序配置，这是设计综合的一部分。配置允许将超级可配置HIU制作成几个可能的专用HIU中的任何一个。此配置在设计阶段执行，不适用于现场应用。旨在消除特定设计中不需要的功能块的优化，并简化和修改其他功能块允许有效配置这些其他类型的HIU。为特定需要配置HIU可以显着节省硅面积和功耗。

8. 发明授权

US07325178B2 Programmable built in self test of memory 有权
标题翻译：可编程内置自检内存
公开(公告)号：US07325178B2
公开(公告)日：2008-01-29
申请号：US11003206
申请日：2004-12-03
申请人： Raguram Damodaran , Timothy D. Anderson , Sanjive Agarwala , Joel J. Graber
发明人： Raguram Damodaran , Timothy D. Anderson , Sanjive Agarwala , Joel J. Graber
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/16
摘要： The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.
摘要翻译：内存测试的pBIST解决方案是一个平衡的面向硬件的软件解决方案。 pBIST硬件提供对允许背靠背访问的流水线逻辑中的所有存储器和其他这样的逻辑（例如寄存器文件）的访问。该方法然后让用户通过类似CPU的逻辑访问该逻辑，其中程序员可以对任何算法进行编码，以定位所需的任何内存测试技术。由于芯片内部的硬件速度被使用，因此可以提供全部设备速度功能。类似CPU的硬件可以进行编程，并且可以在磁带输出之后开发和执行算法，同时在芯片形式的器件上进行测试。

9. 发明授权

US08560896B2 Priority based exception mechanism for multi-level cache controller 有权
标题翻译：多级缓存控制器基于优先级的异常机制
公开(公告)号：US08560896B2
公开(公告)日：2013-10-15
申请号：US13245164
申请日：2011-09-26
申请人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
发明人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
IPC分类号： G06F11/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.
摘要翻译：本发明是一种异常优先仲裁单元，其在相同的周期内被接收时，根据固定层次来优先考虑存储器访问许可故障和数据异常信号。 CPU内存访问权限错误优先于直接内存访问许可故障的DMA内存访问权限错误。任何存储器访问权限故障都优先于数据异常信号。不可修正的数据异常信号优先于可纠正的数据异常信号。

10. 发明授权

US08532247B2 Integer and half clock step division digital variable clock divider 有权
标题翻译：整数和半时钟分频数字可变时钟分频器
公开(公告)号：US08532247B2
公开(公告)日：2013-09-10
申请号：US13247265
申请日：2011-09-28
申请人： Ramakrishnan Venkatasubramanian , Anthony Lell , Raguram Damodaran
发明人： Ramakrishnan Venkatasubramanian , Anthony Lell , Raguram Damodaran
IPC分类号： H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A clock divider divides a high speed input clock signal by an odd, even or fractional divide ratio. The clock divider receives a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates a fractional divide ratio when one and an integral divide ratio when zero. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. The clock divider synthesizes one period of an output clock signal in response to each assertion of the count indicator for a fractional divide ratio and synthesizes one period of the output clock signal in response to two assertions of the count indicator for an integral divide ratio.
摘要翻译：时钟分频器将高速输入时钟信号除以奇数，偶数或分数分频比。时钟分频器接收代表分频比N的除法因子值F，其中N可以是奇数或偶数整数。一个分数指示符表示当零和一个积分分频比为零时的分数分频比。当N为偶数时，每N / 2个输入时钟周期，计数指示器被置位。当N为奇数时，计数指示灯交替显示N / 2个输入时钟周期，然后1 + N / 2个输入时钟周期。时钟分频器响应于分数分频比的计数指示器的每个断言而合成输出时钟信号的一个周期，并响应于积分分频比的计数指示符的两个断言来合成输出时钟信号的一个周期。

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