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61. 发明申请

US20080056124A1 Using TCP/IP offload to accelerate packet filtering 有权
标题翻译：使用TCP / IP卸载来加速包过滤
公开(公告)号：US20080056124A1
公开(公告)日：2008-03-06
申请号：US10875013
申请日：2004-06-23
申请人： Sameer Nanda , Radoslav Danilak , Paul J. Gyugyi , Thomas A. Maufer , Paul J. Sidenblad , Ashutosh K. Jha , Anand Rajagopalan
发明人： Sameer Nanda , Radoslav Danilak , Paul J. Gyugyi , Thomas A. Maufer , Paul J. Sidenblad , Ashutosh K. Jha , Anand Rajagopalan
IPC分类号： H04L12/26
CPC分类号： H04L69/166 , H04L29/06 , H04L69/10 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/22
摘要： A method and apparatus for filtering a packet on a connection within a computing system. In one embodiment, the method includes: receiving the packet; delegating the packet to an offload unit for filtering the packet; and determining, by the offload unit, whether the connection is a delegated connection.
摘要翻译：一种用于过滤计算系统内的连接上的分组的方法和装置。在一个实施例中，该方法包括：接收该分组; 将分组委托给用于过滤分组的卸载单元; 以及由所述卸载单元确定所述连接是否是委托连接。

62. 发明授权

US07117421B1 Transparent error correction code memory system and method 有权
标题翻译：透明纠错码存储系统及方法
公开(公告)号：US07117421B1
公开(公告)日：2006-10-03
申请号：US10159460
申请日：2002-05-31
申请人： Radoslav Danilak
发明人： Radoslav Danilak
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G06F11/1008
摘要： The present invention provides flexible and efficient memory configuration that is capable of economically addressing both resource consumption and ECC concerns. A memory system facilitates transparent ECC operations without dedicated ECC connections. A first dynamic random access memory structure stores data, wherein the data connections to the memory system are limited to the width of the first dynamic random access memory structure. A second dynamic random access memory structure dedicated to storing error correction code information, wherein the error correction code information is accessed via the data connections. In one exemplary implementation, the first memory structure and the second memory structure the data and ECC are included in the same memory bank. In an alternate implementation, the first memory structure and the second memory structure the data and ECC are included in the different memory banks and are accessed in parallel.
摘要翻译：本发明提供了能够经济地解决资源消耗和ECC问题的灵活和有效的存储器配置。存储器系统促进透明ECC操作，而不需要专门的ECC连接。第一动态随机存取存储器结构存储数据，其中到存储器系统的数据连接被限制到第一动态随机存取存储器结构的宽度。专用于存储纠错码信息的第二动态随机存取存储器结构，其中通过数据连接访问纠错码信息。在一个示例性实现中，第一存储器结构和第二存储器结构将数据和ECC包括在同一存储体中。在替代实现中，第一存储器结构和第二存储器结构将数据和ECC包括在不同的存储体中并且被并行访问。

63. 发明授权

US08935595B2 LDPC erasure decoding for flash memories 有权
标题翻译：闪存的LDPC擦除解码
公开(公告)号：US08935595B2
公开(公告)日：2015-01-13
申请号：US13583617
申请日：2011-03-11
申请人： Hao Zhong , Yan Li , Radoslav Danilak , Earl T Cohen
发明人： Hao Zhong , Yan Li , Radoslav Danilak , Earl T Cohen
IPC分类号： G06F11/10 , G11C11/56 , G11C16/10 , G11C16/26 , H03M13/11 , H03M13/37
CPC分类号： H03M13/3715 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C29/52 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/373 , H03M13/6502
摘要： A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.
摘要翻译：固态盘（SSD）控制器使用LDPC解码来实现具有改进的延迟和/或纠错能力的闪速存储器访问。使用BER小于预定值的SLC闪速存储器，SSD控制器使用1位读（单读）硬判决LDPC解码器访问闪速存储器。如果硬判决LDPC解码器检测到不可校正的错误，则SSD控制器使用1.5位读（两读）擦除判决LDPC解码器来访问闪速存储器。对于具有两个其它预定值之间的原始BER的闪速存储器，SSD控制器省略硬判决LDPC解码器的使用，并且仅使用擦除判决LDPC解码器来访问闪速存储器。 SSD控制器的变化类似地访问MLC闪存。一些SSD控制器基于动态解码器选择标准动态地在硬判决和基于擦除的解码器之间切换。

64. 发明授权

US08929066B2 Chassis with separate thermal chamber for solid state memory 有权
标题翻译：底盘配有独立的热室，用于固态存储器
公开(公告)号：US08929066B2
公开(公告)日：2015-01-06
申请号：US13597110
申请日：2012-08-28
申请人： Pinchas Herman , Radoslav Danilak
发明人： Pinchas Herman , Radoslav Danilak
IPC分类号： H05K7/20
CPC分类号： G06F1/20 , H05K7/1487 , H05K7/20727
摘要： A chassis for a network storage system contains a first thermal chamber that houses conventional electronic components and a second thermal chamber that houses non-volatile solid state memory such as flash memory. A cooling system keeps the electronics in first thermal chamber below their maximum junction temperature. Meanwhile, a temperature regulating system maintains the solid state memory in the second thermal chamber within a range of a preferred operating temperature selected to extend the lifetime and/or improve the reliability of the solid state memory. Thus, the chassis provides dual zone temperature control to improve performance of the network storage system.
摘要翻译：用于网络存储系统的底盘包含容纳常规电子部件的第一热室和容纳诸如闪存之类的非易失性固态存储器的第二热室。冷却系统将电子器件保持在第一个热室内，达到最大结温。同时，温度调节系统将第二热室中的固态存储器保持在所选择的优选工作温度的范围内，以延长使用寿命和/或提高固态存储器的可靠性。因此，机箱提供双区域温度控制，以提高网络存储系统的性能。

65. 发明授权

US08848383B2 Motherboard with card guide cutouts 有权
标题翻译：主板带导卡切口
公开(公告)号：US08848383B2
公开(公告)日：2014-09-30
申请号：US13597051
申请日：2012-08-28
申请人： Pinchas Herman , Radoslav Danilak
发明人： Pinchas Herman , Radoslav Danilak
IPC分类号： H05K7/14 , H05K7/12
CPC分类号： G06F1/185 , H05K7/1418 , H05K7/1487
摘要： A system for mounting a flash blade in a storage system includes a motherboard with a series of card guide cutouts for aligning flash blades. A flash blade can be aligned perpendicular to the motherboard and aligned parallel to adjacent flash blades by inserting the flash blade into one of the card guide cutouts and connecting the flash blade to a connector at one end of the cutout. This beneficially aligns the flash blade while making efficient use of the available vertical space within a chassis. The flash blade can also extend through the cutout to the other side of the motherboard. The efficient use of vertical space enables an increase in the number of solid state memory can be added to the flash blade relative to conventional designs, thereby improving capacity.
摘要翻译：用于将闪存刀片安装在存储系统中的系统包括具有用于对准闪存刀片的一系列卡引导切口的母板。闪光灯片可以垂直于母板对准，并且平行于相邻的闪光灯片对准，将闪光灯片插入其中一个卡片导向槽中，并将闪光片连接到切口一端的连接器。这有利地使闪光灯片对准，同时有效利用机箱内的可用垂直空间。闪光灯片还可以延伸通过切口到主板的另一侧。垂直空间的有效利用使得能够相对于常规设计可以增加固态存储器的数量，从而提高容量。

66. 发明授权

US08751732B2 System and method for increasing capacity, performance, and flexibility of flash storage 有权
标题翻译：提高闪存存储容量，性能和灵活性的系统和方法
公开(公告)号：US08751732B2
公开(公告)日：2014-06-10
申请号：US13620424
申请日：2012-09-14
申请人： Radoslav Danilak , Michael J. S. Smith , Suresh Rajan
发明人： Radoslav Danilak , Michael J. S. Smith , Suresh Rajan
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F3/0679 , G06F13/385
摘要： In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.
摘要翻译：在一个实施例中，接口电路被配置为耦合到一个或多个闪存设备，并且还被配置为耦合到主机系统。接口电路被配置为向主机系统呈现至少一个虚拟闪存设备，其中接口电路被配置为使用接口电路耦合到的一个或多个闪存设备来实现虚拟闪存设备。

67. 发明授权

US08417852B2 Uploading TCP frame data to user buffers and buffers in system memory 有权
标题翻译：将TCP帧数据上传到系统内存中的用户缓冲区和缓冲区
公开(公告)号：US08417852B2
公开(公告)日：2013-04-09
申请号：US10731063
申请日：2003-12-09
申请人： Anand Rajagopalan , Radoslav Danilak , Paul J. Gyugyi , Ashutosh K. Jha , Thomas A. Maufer , Sameer Nanda , Paul J. Sidenblad
发明人： Anand Rajagopalan , Radoslav Danilak , Paul J. Gyugyi , Ashutosh K. Jha , Thomas A. Maufer , Sameer Nanda , Paul J. Sidenblad
IPC分类号： G06F13/38
CPC分类号： H04L69/16 , H04L29/06 , H04L47/12 , H04L47/225 , H04L69/10 , H04L69/12 , H04L69/161 , H04L69/163 , H04L69/166 , H04L69/22
摘要： A system and methods of uploading payload data to user buffers in system memory and of uploading partially processed frame data to legacy buffers allocated in Operating System memory space are described. User buffers are stored in a portion of system memory allocated to an application program, therefore data stored in user buffers does not need to be copied from another portion of system memory to the portion of system memory allocated to the application program. When partially processed frame data is uploaded by hardware to a legacy buffer in system memory, a tag, uniquely identifying the legacy buffer location is transferred by the hardware to a TCP stack, enabling the TCP stack to locate the legacy buffer.
摘要翻译：描述了将有效载荷数据上传到系统存储器中的用户缓冲器并且将部分处理的帧数据上传到在操作系统存储器空间中分配的传统缓冲器的系统和方法。用户缓冲器存储在分配给应用程序的系统存储器的一部分中，因此存储在用户缓冲器中的数据不需要从系统存储器的另一部分复制到分配给应用程序的系统存储器的部分。当部分处理的帧数据由硬件上传到系统存储器中的传统缓冲器时，唯一地标识传统缓冲器位置的标签由硬件传送到TCP堆栈，使TCP堆栈能够定位传统缓冲区。

68. 发明授权

US08356142B1 Memory controller for non-sequentially prefetching data for a processor of a computer system 有权
标题翻译：用于计算机系统的处理器的非顺序预取数据的存储器控制器
公开(公告)号：US08356142B1
公开(公告)日：2013-01-15
申请号：US10712520
申请日：2003-11-12
申请人： Radoslav Danilak
发明人： Radoslav Danilak
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/0862
摘要： A memory controller for non-sequentially prefetching data for a processor of a computer system. The memory controller performs a method including the step of storing a plurality of address pairs in a table data structure, wherein the address pairs include a first address and a second address. The first address and the second address are non-sequential as fetched by a processor of a computer system. The address pairs are prioritized in accordance with a frequency of use for each of the address pairs. A system memory of the computer system is accessed and a plurality of cache lines corresponding to the address pairs are stored in a prefetch cache. Upon a cache hit during a subsequent access by the processor, data is transferred from the cache lines stored in the prefetch cache to the processor.
摘要翻译：一种用于计算机系统的处理器的非顺序预取数据的存储器控制器。存储器控制器执行包括在表数据结构中存储多个地址对的步骤的方法，其中地址对包括第一地址和第二地址。第一地址和第二地址是不连续的，由计算机系统的处理器取出。地址对根据每个地址对的使用频率进行优先排列。访问计算机系统的系统存储器，并且将与地址对相对应的多个高速缓存行存储在预取高速缓存中。在处理器随后访问期间的缓存命中时，数据从存储在预取高速缓存中的高速缓存行传送到处理器。

69. 发明授权

US08339881B2 Techniques for increasing a lifetime of blocks of memory 有权
公开(公告)号：US08339881B2
公开(公告)日：2012-12-25
申请号：US13042242
申请日：2011-03-07
申请人： Radoslav Danilak
发明人： Radoslav Danilak
IPC分类号： G11C7/00
CPC分类号： G06F3/0616 , G06F3/0608 , G06F3/0631 , G06F3/064 , G06F3/0649 , G06F3/0652 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F11/1072 , G06F12/023 , G06F12/0246 , G06F2212/1044 , G06F2212/7201 , G06F2212/7202 , G06F2212/7205 , G06F2212/7211 , G11C14/009 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/349 , G11C16/3495 , G11C17/00 , G11C29/04 , G11C29/52
摘要： Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.

70. 发明申请

US20120311378A1 Techniques for increasing a lifetime of blocks of memory 有权
标题翻译：增加存储块寿命的技术
公开(公告)号：US20120311378A1
公开(公告)日：2012-12-06
申请号：US13572257
申请日：2012-08-10
申请人： Radoslav Danilak
发明人： Radoslav Danilak
IPC分类号： G06F11/16
CPC分类号： G06F3/0616 , G06F3/0608 , G06F3/0631 , G06F3/064 , G06F3/0649 , G06F3/0652 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F11/1072 , G06F12/023 , G06F12/0246 , G06F2212/1044 , G06F2212/7201 , G06F2212/7202 , G06F2212/7205 , G06F2212/7211 , G11C14/009 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/349 , G11C16/3495 , G11C17/00 , G11C29/04 , G11C29/52
摘要： Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.
摘要翻译：描述了用于增加存储块的寿命的技术。在操作中，至少部分地基于分别擦除每个块的相应次数来计算每个块的各自的预期寿命得分，并且还至少部分地基于影响寿命的至少一个其他因素的块。至少部分地基于相应的寿命预期得分中的至少一些确定写入和回收块的命令。擦除和写入的块的总量被最小化，同时块之间的寿命预期得分变化相等。

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