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61. 发明授权

US07355429B2 On-chip power supply noise detector 失效
标题翻译：片上电源噪声检测器
公开(公告)号：US07355429B2
公开(公告)日：2008-04-08
申请号：US11089215
申请日：2005-03-24
申请人： Keith A. Jenkins , Anuja Sehgal , Peilin Song
发明人： Keith A. Jenkins , Anuja Sehgal , Peilin Song
IPC分类号： G01R31/02
CPC分类号： G01R31/3004 , G01R19/16552
摘要： Techniques for on-chip detection of integrated circuit power supply noise are disclosed. By way of example, a technique for monitoring a power supply line in an integrated circuit includes the following steps/operations. A first signal and a second signal are preconditioned. The first signal is representative of a voltage of the power supply line being monitored. The second signal is representative of a voltage of a reference power supply line. Preconditioning includes shifting respective levels of the voltages such that the voltages are within an output voltage range of comparator circuitry. Then, the preconditioned first signal and the preconditioned second signal are compared in accordance with the comparator circuitry. Comparison includes detecting when a difference exists between the voltage level of the preconditioned first signal and the voltage level of the preconditioned second signal.
摘要翻译：公开了片上检测集成电路电源噪声的技术。作为示例，用于监视集成电路中的电源线的技术包括以下步骤/操作。第一信号和第二信号被预处理。第一信号代表被监测的电源线的电压。第二信号代表参考电源线的电压。预处理包括移动电压的各个电平，使得电压在比较器电路的输出电压范围内。然后，根据比较器电路对预处理的第一信号和预处理的第二信号进行比较。比较包括检测预处理的第一信号的电压电平与预处理的第二信号的电压电平之间的差异。

62. 发明申请

US20080036477A1 ON-CHIP POWER SUPPLY NOISE DETECTOR 失效
标题翻译：片上电源噪声检测器
公开(公告)号：US20080036477A1
公开(公告)日：2008-02-14
申请号：US11874528
申请日：2007-10-18
申请人： Keith Jenkins , Anuja Sehgal , Peilin Song
发明人： Keith Jenkins , Anuja Sehgal , Peilin Song
IPC分类号： G01R27/08
CPC分类号： G01R31/3004 , G01R19/16552
摘要： Techniques for on-chip detection of integrated circuit power supply noise are disclosed. By way of example, a technique for monitoring a power supply line in an integrated circuit includes the following steps/operations. A first signal and a second signal are preconditioned. The first signal is representative of a voltage of the power supply line being monitored. The second signal is representative of a voltage of a reference power supply line. Preconditioning includes shifting respective levels of the voltages such that the voltages are within an input voltage range of comparator circuitry. Then, the preconditioned first signal and the preconditioned second signal are compared in accordance with the comparator circuitry. Comparison includes detecting when a difference exists between the voltage level of the preconditioned first signal and the voltage level of the preconditioned second signal.
摘要翻译：公开了片上检测集成电路电源噪声的技术。作为示例，用于监视集成电路中的电源线的技术包括以下步骤/操作。第一信号和第二信号被预处理。第一信号代表被监测的电源线的电压。第二信号代表参考电源线的电压。预处理包括移动电压的各个电平，使得电压在比较器电路的输入电压范围内。然后，根据比较器电路对预处理的第一信号和预处理的第二信号进行比较。比较包括检测预处理的第一信号的电压电平与预处理的第二信号的电压电平之间的差异。

63. 发明申请

US20050188290A1 Method and structure for picosecond-imaging-circuit-analysis based built-in-self-test diagnostic 失效
标题翻译：基于皮秒成像 - 电路分析的内置自检诊断方法和结构
公开(公告)号：US20050188290A1
公开(公告)日：2005-08-25
申请号：US10780878
申请日：2004-02-19
申请人： Franco Motika , Peilin Song
发明人： Franco Motika , Peilin Song
IPC分类号： G01R31/28 , G01R31/311 , G01R31/3185
CPC分类号： G01R31/318547 , G01R31/311
摘要： A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.
摘要翻译：测试，诊断和监视电子电路的操作中的至少一个的方法（和结构）包括中断用于为电路的正常操作提供时钟的时钟信号，并且使用第二时钟信号重复循环通过电路的预定操作周期。

64. 发明授权

US06816990B2 VLSI chip test power reduction 失效
标题翻译： VLSI芯片测试功耗降低
公开(公告)号：US06816990B2
公开(公告)日：2004-11-09
申请号：US10058485
申请日：2002-01-28
申请人： Peilin Song , Timothy J. Koprowski , Ulrich Baur , Franco Motika
发明人： Peilin Song , Timothy J. Koprowski , Ulrich Baur , Franco Motika
IPC分类号： G01R3128
CPC分类号： G01R31/31721 , G01R31/31707 , G01R31/318307 , G01R31/318502 , G01R31/318522 , G01R31/3187
摘要： LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.
摘要翻译： LBIST和加权LBIST测试在测试对象的不同部分上同时进行。这种新的测试方法和设计变化与传统的测试策略相比，测试覆盖率和测试时间都大大降低。它可以应用于晶圆，芯片，MCM和系统测试级别。最重要的是，它不需要新的支持工具。当前的测试软件将与传统的测试策略一样工作。在相同测试会话中调度LBIST和加权LBIST测试降低了整体功耗，因为加权LBIST测试比平面LBIST测试消耗的功率少得多。在相同的测试会话中，如果使用加权LBIST测试逻辑的某些部分，而使用LBIST测试其他部分，则电路元件在任何给定时间消耗的功率降低。

65. 发明授权

US07961307B2 Angular spectrum tailoring in solid immersion microscopy for circuit analysis 失效
标题翻译：用于电路分析的固体浸液显微镜中的角度光谱裁剪
公开(公告)号：US07961307B2
公开(公告)日：2011-06-14
申请号：US12911781
申请日：2010-10-26
申请人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
发明人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
IPC分类号： G01N21/00
CPC分类号： G01R31/311
摘要： A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译：用于定位半导体芯片中的故障的结构。芯片包括电介质互连上的衬底。包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。

66. 发明申请

US20090189630A1 ANGULAR SPECTRUM TAILORING IN SOLID IMMERSION MICROSCOPY FOR CIRCUIT ANALYSIS 失效
标题翻译：用于电路分析的固体显微镜中的角度光谱定标
公开(公告)号：US20090189630A1
公开(公告)日：2009-07-30
申请号：US12020157
申请日：2008-01-25
申请人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
发明人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
IPC分类号： G01R31/26
CPC分类号： G01R31/311
摘要： A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译：一种用于定位半导体芯片中的故障的方法和结构。芯片包括电介质互连上的衬底。包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。

67. 发明申请

US20080129325A1 ON-CHIP DETECTION OF POWER SUPPLY VULNERABILITIES 有权
标题翻译：电源漏电检测
公开(公告)号：US20080129325A1
公开(公告)日：2008-06-05
申请号：US12013833
申请日：2008-01-14
申请人： Frank D. Ferraiolo , Anuja Sehgal , Peilin Song , Michael A. Sperling
发明人： Frank D. Ferraiolo , Anuja Sehgal , Peilin Song , Michael A. Sperling
IPC分类号： G01R31/26
CPC分类号： G01R31/30 , G01R31/2884 , G01R31/3016 , G01R31/31721
摘要： On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.
摘要翻译：片上传感器检测电源漏洞。片内传感器采用敏感延迟链和不敏感延迟链，以检测电源下冲和过冲，而无需外部片外部件。检测到用户定义的阈值之外的下冲和超调。下冲和过冲由两个延迟链的相位相对差异表示。两个延迟链可编程，以检测各种频率。

68. 发明申请

US20080007272A1 ON-CHIP DETECTION OF POWER SUPPLY VULNERABILITIES 有权
公开(公告)号：US20080007272A1
公开(公告)日：2008-01-10
申请号：US11056822
申请日：2005-02-10
申请人： Frank Ferraiolo , Anuja Sehgal , Peilin Song , Michael Sperling
发明人： Frank Ferraiolo , Anuja Sehgal , Peilin Song , Michael Sperling
IPC分类号： G01R27/28
CPC分类号： G01R31/30 , G01R31/2884 , G01R31/3016 , G01R31/31721
摘要： On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.

69. 发明授权

US07308626B2 Method and structure for picosecond-imaging-circuit-analysis based built-in-self-test diagnostic 失效
标题翻译：基于皮秒成像 - 电路分析的内置自检诊断方法和结构
公开(公告)号：US07308626B2
公开(公告)日：2007-12-11
申请号：US10780878
申请日：2004-02-19
申请人： Franco Motika , Peilin Song
发明人： Franco Motika , Peilin Song
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/311
摘要： A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.
摘要翻译：测试，诊断和监视电子电路的操作中的至少一个的方法（和结构）包括中断用于为电路的正常操作提供时钟的时钟信号，并且使用第二时钟信号重复循环通过电路的预定操作周期。

70. 发明授权

US07095264B2 Programmable jitter signal generator 有权
标题翻译：可编程抖动信号发生器
公开(公告)号：US07095264B2
公开(公告)日：2006-08-22
申请号：US10725847
申请日：2003-12-02
申请人： Keith A. Jenkins , Jien-Chung Lo , Peilin Song , Tian Xia
发明人： Keith A. Jenkins , Jien-Chung Lo , Peilin Song , Tian Xia
IPC分类号： H03H11/26
CPC分类号： G01R31/31709 , G01R31/31727 , G06F1/03 , H03K5/133 , H03K5/1506 , H03K2005/00058
摘要： A programmable jitter signal generator is provided that includes a jitter distribution control unit, a selection unit in signal communication with the jitter distribution control unit, and a delay unit in signal communication with the selection unit; and a corresponding method of generating a programmable jitter signal includes programming a control unit, receiving a reference signal, delaying the received reference signal by a multiple of a base time increment, and selecting a delayed reference signal delayed by a desired multiple of the base time increment in accordance with the programmed control unit.
摘要翻译：提供了一种可编程抖动信号发生器，其包括抖动分布控制单元，与抖动分布控制单元进行信号通信的选择单元，以及与选择单元进行信号通信的延迟单元; 并且产生可编程抖动信号的相应方法包括编程控制单元，接收参考信号，将接收到的参考信号延迟基准时间增量的倍数，以及选择延迟基准时间的期望倍数的延迟参考信号根据编程的控制单元增量。

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