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61. 发明授权

US06785782B1 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules 有权
标题翻译：增加具有不匹配内存模块的每个模块内存系统带宽的技术
公开(公告)号：US06785782B1
公开(公告)日：2004-08-31
申请号：US09948905
申请日：2001-09-10
申请人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel , Ely K. Tsern
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel , Ely K. Tsern
IPC分类号： G06F1200
CPC分类号： G11C7/1048 , G11C5/04 , G11C5/066 , G11C7/1012
摘要： Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory module for storing data thereon. The memory module comprises a memory component having a first set of interface connections for providing access to a memory core of the memory component and a second set of interface connections for providing access to the memory core of the memory component. The memory module also comprises memory access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.
摘要翻译：公开了用于增加具有不匹配的存储器模块的每模块模块存储器系统中的带宽的技术。在一个示例性实施例中，通过用于在其上存储数据的存储器模块实现这些技术。存储器模块包括具有用于提供对存储器组件的存储器核心的访问的第一组接口连接的存储器组件和用于提供对存储器组件的存储器核心的访问的第二组接口连接。存储器模块还包括用于在第一模式之间进行选择的存储器访问电路，其中存储器核心的第一部分可通过第一组接口连接访问，并且存储器核心的第二部分可通过第二组接口连接访问，以及第二模式，其中存储器核心的第一部分和第二部分都可通过第一组接口连接访问。

62. 发明授权

US08644419B2 Periodic calibration for communication channels by drift tracking 有权
标题翻译：通过漂移跟踪定期通信通道
公开(公告)号：US08644419B2
公开(公告)日：2014-02-04
申请号：US13452543
申请日：2012-04-20
申请人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04L27/00
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
摘要翻译：提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量在参数中漂移，并根据测量的漂移更新操作值。与第一校准序列相比，第二校准序列使用较少的通信信道资源。在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。

63. 发明授权

US08364926B2 Memory module with reduced access granularity 有权
标题翻译：具有减少访问粒度的内存模块
公开(公告)号：US08364926B2
公开(公告)日：2013-01-29
申请号：US13408950
申请日：2012-02-29
申请人： Craig E. Hampel , Frederick A. Ware
发明人： Craig E. Hampel , Frederick A. Ware
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F12/1081 , G06F13/1663 , G06F13/1678 , G06F13/1684 , G06F13/28 , G06F13/4243 , G06F2212/656 , G11C5/04 , G11C7/1012 , G11C7/1045 , G11C7/1075 , H05K1/181 , H05K2201/09227 , H05K2201/10159 , Y02D10/14 , Y02D10/151 , Y02P70/611
摘要： A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.
摘要翻译：具有减小的访问粒度的存储器模块。存储器模块包括其上具有信号线的衬底，其形成控制路径和第一和第二数据路径，并且还包括共同耦合到控制路径并分别耦合到第一和第二数据路径的第一和第二存储器件。第一和第二存储器件包括控制电路，用于响应于第一和第二存储器访问命令，经由控制路径接收相应的第一和第二存储器访问命令并且执行第一和第二数据路径上的并发数据传输。

64. 发明申请

US20120281489A1 Low Power Memory Device 审中-公开
标题翻译：低功耗存储器件
公开(公告)号：US20120281489A1
公开(公告)日：2012-11-08
申请号：US13466082
申请日：2012-05-07
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C5/14 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C8/08 , G11C8/12 , G11C11/4063 , G11C11/4076 , G11C11/4085 , G11C2207/2227
摘要： “A method of operation within a memory device comprises receiving address information and corresponding enable information. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state. The states of the first and second enable values may be separately controlled.”
摘要翻译：存储器件内的操作方法包括接收地址信息和相应的使能信息。地址信息包括指定存储器件的存储阵列内的存储单元行的行地址，并且使能信息包括分别对应于存储单元行内的第一和第二存储位置的第一和第二使能值。如果第一使能值处于使能状态，则该方法包括在第一存储位置和读出放大器电路之间选择性地传送数据，并且如果第二使能值处于使能状态，则在第二存储位置和读出放大器电路之间传送数据。可以单独控制第一和第二使能值的状态。

65. 发明申请

US20120155526A1 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 有权
标题翻译：通信通道校准条件
公开(公告)号：US20120155526A1
公开(公告)日：2012-06-21
申请号：US13409534
申请日：2012-03-01
申请人： FREDERICK A. WARE , Richard E. Perego , Craig E. Hampel
发明人： FREDERICK A. WARE , Richard E. Perego , Craig E. Hampel
IPC分类号： H04B17/00
CPC分类号： H04L7/0016 , G11C7/04 , G11C2207/2254 , H04L7/0087 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
摘要翻译：方法和系统提供在通信信道的正常操作期间不时地执行校准周期。校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。使用第二组件上的接收器从通信链路接收校准模式。响应于所接收的校准模式来确定通信信道的参数的校准值。校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

66. 发明申请

US20120134084A1 Memory Modules and Devices Supporting Configurable Core Organizations 有权
标题翻译：支持可配置核心组织的内存模块和设备
公开(公告)号：US20120134084A1
公开(公告)日：2012-05-31
申请号：US13365890
申请日：2012-02-03
申请人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： H05K7/00
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.
摘要翻译：描述了组织在存储器子部分中并且包括可配置路由以支持多个数据宽度配置的存储器设备。相对窄的宽度配置加载较少的读出放大器，导致相对较窄的存储器配置的功率消耗减少。还描述了将宽度选择信息传送到可配置的存储装置并支持多个宽度配置的点对点数据接口的存储器控制器。

67. 发明申请

US20120039138A1 ASYNCHRONOUS PIPELINED MEMORY ACCESS 失效
标题翻译：异步管道存储器访问
公开(公告)号：US20120039138A1
公开(公告)日：2012-02-16
申请号：US13281436
申请日：2011-10-26
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18 , G11C7/06 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： A plurality of control signals are asserted within an asynchronous integrated circuit memory device in response to each transition of a memory access initiation signal to effect pipelined memory access operations.
摘要翻译：多个控制信号在异步集成电路存储器件内响应于存储器访问启动信号的每个转换而被执行以实现流水线存储器访问操作。

68. 发明授权

US08059476B2 Control component for controlling a delay interval within a memory component 有权
标题翻译：用于控制存储器组件内的延迟间隔的控制组件
公开(公告)号：US08059476B2
公开(公告)日：2011-11-15
申请号：US12942907
申请日：2010-11-09
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

69. 发明申请

US20110055509A1 CONTROL COMPONENT FOR CONTROLLING A DELAY INTERVAL WITHIN A MEMORY COMPONENT 有权
标题翻译：用于控制存储器组件中的延迟间隔的控制组件
公开(公告)号：US20110055509A1
公开(公告)日：2011-03-03
申请号：US12942907
申请日：2010-11-09
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G06F12/00 , G11C7/22
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

70. 发明申请

US20100223426A1 Variable-width memory 有权
标题翻译：可变宽度内存
公开(公告)号：US20100223426A1
公开(公告)日：2010-09-02
申请号：US12631614
申请日：2009-12-04
申请人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/02
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
摘要翻译：描述了存储器系统，其中存储器核心组织随设备宽度而变化。所访问的物理存储器组的数量随着器件宽度而减少，导致相对较窄的存储器配置的功率消耗减少。增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

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