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61. 发明授权

US6028360A Semiconductor integrated circuit device in which a conductive film is formed over a trap film which in turn is formed over a titanium film 失效
标题翻译：半导体集成电路器件，其中导电膜形成在捕获膜上，其又形成在钛膜上
公开(公告)号：US6028360A
公开(公告)日：2000-02-22
申请号：US106074
申请日：1998-06-29
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L21/8242 , H01L23/522 , H01L23/48 , H01L27/108
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
摘要翻译：根据以下步骤形成半导体器件。通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

62. 发明授权

US6023084A Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance and method of manufacturing same 有权
标题翻译：包括具有增加的信息存储电容的存储单元的存储器件的半导体集成电路器件及其制造方法
公开(公告)号：US6023084A
公开(公告)日：2000-02-08
申请号：US174332
申请日：1998-10-19
申请人： Yoshitaka Tadaki , Jun Murata , Toshihiro Sekiguchi , Hideo Aoki , Keizo Kawakita , Hiroyuki Uchiyama , Michio Nishimura , Michio Tanaka , Yuji Ezaki , Kazuhiko Saitoh , Katsuo Yuhara , Songsu Cho
发明人： Yoshitaka Tadaki , Jun Murata , Toshihiro Sekiguchi , Hideo Aoki , Keizo Kawakita , Hiroyuki Uchiyama , Michio Nishimura , Michio Tanaka , Yuji Ezaki , Kazuhiko Saitoh , Katsuo Yuhara , Songsu Cho
IPC分类号： H01L21/3205 , H01L21/8242 , H01L23/52 , H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/10817 , H01L2924/0002
摘要： A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.
摘要翻译：半导体存储器件具有半导体衬底和设置在字线导体和位线导体之间的交叉点处的存储单元。每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，并且相邻两个存储单元的晶体管的第二半导体区域连接到各信息存储电容器。形成在一个位线导体下方的一系列存储单元对单元结构相对于分别在一个位线导体的相对侧上相邻的相邻第一和第二位线导体下形成的一系列存储单元对单元结构位置移位，使得形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于邻近位线连接导体形成在一个位线导体下的存储单元对单元结构。

63. 发明授权

US5981369A Semiconductor integrated circuit device and process for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5981369A
公开(公告)日：1999-11-09
申请号：US865864
申请日：1997-05-30
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Kazuhiko Kajigaya , Hideo Aoki , Isamu Asano
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Kazuhiko Kajigaya , Hideo Aoki , Isamu Asano
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/52 , H01L27/092 , H01L27/10 , H01L27/108 , H01L21/44
CPC分类号： H01L21/823871 , H01L21/76877 , H01L21/76897 , H01L21/823814 , H01L21/76849 , H01L21/76853 , H01L27/10855 , H01L27/10894
摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.
摘要翻译：在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积在形成MISFET之后的步骤中，在半导体基板上淀积500℃以下的温度。此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

64. 发明授权

US5933726A Method of forming a semiconductor device have a screen stacked cell capacitor 失效
标题翻译：形成半导体器件的方法具有屏幕堆叠单元电容器
公开(公告)号：US5933726A
公开(公告)日：1999-08-03
申请号：US709203
申请日：1996-08-27
申请人： Michio Nishimura , Kazuhiko Saitoh , Masayuki Yasuda , Takashi Hayakawa , Michio Tanaka , Yuji Ezaki , Katsuo Yuhara , Minoru Ohtsuka , Toshikazu Kumai , Songsu Cho , Toshiyuki Kaeriyama , Keizo Kawakita , Toshihiro Sekiguchi , Yoshitaka Tadaki , Jun Murata , Hideo Aoki , Akihiko Konno , Kiyomi Katsuyama , Takafumi Tokunaga , Yoshimi Torii
发明人： Michio Nishimura , Kazuhiko Saitoh , Masayuki Yasuda , Takashi Hayakawa , Michio Tanaka , Yuji Ezaki , Katsuo Yuhara , Minoru Ohtsuka , Toshikazu Kumai , Songsu Cho , Toshiyuki Kaeriyama , Keizo Kawakita , Toshihiro Sekiguchi , Yoshitaka Tadaki , Jun Murata , Hideo Aoki , Akihiko Konno , Kiyomi Katsuyama , Takafumi Tokunaga , Yoshimi Torii
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.
摘要翻译：诸如动态RAM的半导体器件及其制造方法。在p型硅衬底（1）的顶部上沿着取向方向以规定的间隔放置多个堆叠的电池电容器。每个电容器具有几乎垂直的圆柱形下电极（圆柱形多晶硅层（96）），电介质膜（氮化硅膜（77））和上电极（由多晶硅制成的板电极（78））。排列方向上的间隔小于下电极的内径。

65. 发明授权

US5831300A Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance and method of manufacturing same 失效
标题翻译：包括具有增加的信息存储电容的存储单元的存储器件的半导体集成电路器件及其制造方法
公开(公告)号：US5831300A
公开(公告)日：1998-11-03
申请号：US731489
申请日：1996-10-16
申请人： Yoshitaka Tadaki , Jun Murata , Toshihiro Sekiguchi , Hideo Aoki , Keizo Kawakita , Hiroyuki Uchiyama , Michio Nishimura , Michio Tanaka , Yuji Ezaki , Kazuhiko Saitoh , Katsuo Yuhara , Songsu Cho
发明人： Yoshitaka Tadaki , Jun Murata , Toshihiro Sekiguchi , Hideo Aoki , Keizo Kawakita , Hiroyuki Uchiyama , Michio Nishimura , Michio Tanaka , Yuji Ezaki , Kazuhiko Saitoh , Katsuo Yuhara , Songsu Cho
IPC分类号： H01L21/3205 , H01L21/8242 , H01L23/52 , H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/10817 , H01L2924/0002
摘要： A semiconductor memory device has a semiconductor substrate, word line conductors and bit line conductors, and memory cells provided at intersections between the word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to the series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.
摘要翻译：半导体存储器件具有半导体衬底，字线导体和位线导体以及设置在字线导体和位线导体之间的交叉点处的存储单元。每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，相邻两个存储单元的晶体管的第二半导体区域连接到相应的两个存储单元的晶体管的第二半导体区域信息存储电容器。形成在一个位线导体下方的一系列存储单元对单元结构相对于分别形成在一个位线导体的相对侧上相邻的第一和第二位线导体之下的一系列存储单元对单元结构位移地移位，形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于与位线连接形成在一个位线导体下的存储单元对单元结构的导体。

66. 发明授权

US5808086A Process for preparing bis (2-hydroxyphenyl-3-benztriazole) methanes 失效
标题翻译：制备双（2-羟基苯基-3-苯并三唑）甲烷的方法
公开(公告)号：US5808086A
公开(公告)日：1998-09-15
申请号：US901347
申请日：1997-07-28
申请人： Naoyuki Sugii , Toshiyuki Yamauchi , Eisuke Kanagawa , Hideo Aoki , Kazuyuki Ishihara
发明人： Naoyuki Sugii , Toshiyuki Yamauchi , Eisuke Kanagawa , Hideo Aoki , Kazuyuki Ishihara
IPC分类号： C07D249/20
CPC分类号： C07D249/20
摘要： A 2-hydroxyphenylbenzotriazole is reacted with a formaldehyde and an amino alcohol in an organic solvent in the presence of a basic catalyst. It is thereby possible to obtain bis(2-hydroxyphenyl-3-benzotriazole) methanes efficiently and at a high yield.
摘要翻译：在碱性催化剂存在下，使2-羟基苯基苯并三唑与甲醛和氨基醇在有机溶剂中反应。从而有可能以高产率获得双（2-羟基苯基-3-苯并三唑）甲烷。

67. 发明授权

US5804479A Method for forming semiconductor integrated circuit device having a capacitor 失效
标题翻译：用于形成具有电容器的半导体集成电路器件的方法
公开(公告)号：US5804479A
公开(公告)日：1998-09-08
申请号：US694665
申请日：1996-08-09
申请人： Hideo Aoki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Keizo Kawakita , Takashi Hayakawa , Katsutoshi Matsunaga , Kazuhiko Saitoh , Michio Nishimura , Minoru Ohtsuka , Katsuo Yuhara , Michio Tanaka , Yuji Ezaki , Toshiyuki Kaeriyama , SongSu Cho
发明人： Hideo Aoki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Keizo Kawakita , Takashi Hayakawa , Katsutoshi Matsunaga , Kazuhiko Saitoh , Michio Nishimura , Minoru Ohtsuka , Katsuo Yuhara , Michio Tanaka , Yuji Ezaki , Toshiyuki Kaeriyama , SongSu Cho
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/822 , H01L21/8239 , H01L21/8242 , H01L27/04 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/1052 , H01L27/105
摘要： The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array. Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.
摘要翻译：当通过在覆盖信息处理的上电极的BPSG膜上布置第一层布线来蚀刻和平坦化氧化硅膜时，提高作为较高海拔部分的存储器阵列的氧化硅膜的回蚀量。仅在外围电路中存储电容元件，但不将其布置在存储器阵列中。因此，获得具有堆叠电容器结构的DRAM，使得存储器阵列和外围电路之间的电平差减小，并且布线和连接孔的形成容易。

68. 发明授权

US5739589A Semiconductor integrated circuit device process for fabricating the same and apparatus for fabricating the same 失效
标题翻译：用于制造该半导体集成电路器件的半导体集成电路器件及其制造方法
公开(公告)号：US5739589A
公开(公告)日：1998-04-14
申请号：US657194
申请日：1996-06-03
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/44 , H01L21/48
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

69. 发明授权

US5202275A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US5202275A
公开(公告)日：1993-04-13
申请号：US496330
申请日：1990-03-20
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在所述衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区和非活性区域的全部表面部分中的方式，在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

70. 发明授权

US4796037A Compact image recording apparatus having an up-side down structure 失效
标题翻译：具有上下结构的紧凑型图像记录装置
公开(公告)号：US4796037A
公开(公告)日：1989-01-03
申请号：US166974
申请日：1988-03-11
申请人： Hiromi Takada , Toshio Shimazaki , Keiji Okamoto , Hideo Aoki
发明人： Hiromi Takada , Toshio Shimazaki , Keiji Okamoto , Hideo Aoki
IPC分类号： G06K15/12 , G01D15/00
CPC分类号： G06K15/12
摘要： A compact laser printer has an up-side down arrangement of components within a machine housing. That is, an optical writing unit is disposed below a rotatably supported photosensitive drum and an image transferring unit is disposed above the photosensitive drum with a developing unit disposed substantially in a side-by-side relationship with the photosensitive drum. A paper feed cassette is located below the optical writing unit when detachably set in position and a paper transportation path extends from the supply end of the paper feed cassette around the developing unit generally in the shape of "U." The machine housing has a pivotally movable portion which may be pivotted open and closed. The photosensitive drum and/or one of a pair of registration rollers may be mounted on the pivotally movable portion.
摘要翻译：紧凑型激光打印机具有机器壳体内的部件的上侧布置。也就是说，光学写入单元设置在可旋转地支撑的感光鼓的下方，并且图像转印单元设置在感光鼓的上方，该显影单元基本上与感光鼓并排地设置。当可拆卸地设置在位置时，供纸盒位于光学写入单元的下方，并且纸张传送路径从供纸盒的供给端围绕显影单元延伸，大致呈“U”形。机器壳体具有可枢转地打开和关闭的可枢转运动的部分。感光鼓和/或一对定位辊中的一个可以安装在可枢转运动的部分上。

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