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61. 发明授权

US08471265B2 Epitaxial substrate with intermediate layers for reinforcing compressive strain in laminated composition layers and manufacturing method thereof 有权
标题翻译：具有用于增强层压组合物层中的压缩应变的中间层的外延衬底及其制造方法
公开(公告)号：US08471265B2
公开(公告)日：2013-06-25
申请号：US13414104
申请日：2012-03-07
申请人： Makoto Miyoshi , Shigeaki Sumiya , Mikiya Ichimura , Sota Maehara , Mitsuhiro Tanaka
发明人： Makoto Miyoshi , Shigeaki Sumiya , Mikiya Ichimura , Sota Maehara , Mitsuhiro Tanaka
IPC分类号： H01L29/205 , H01L21/20 , H01L29/04
CPC分类号： H01L29/2003 , C30B25/186 , C30B29/403 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L29/045 , H01L29/205 , H01L29/7787
摘要： Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes a (111) single crystal Si substrate, a buffer layer, and a crystal layer. The buffer layer is formed of a first lamination unit and a second lamination unit being alternately laminated. The first lamination unit includes a composition modulation layer and a first intermediate layer. The composition modulation layer is formed of a first unit layer and a second unit layer having different compositions being alternately and repeatedly laminated so that a compressive strain exists therein. The first intermediate layer enhances the compressive strain existing in the composition modulation layer. The second lamination unit is a second intermediate layer that is substantially strain-free.
摘要翻译：提供了具有少量翘曲的无裂纹外延基板，其中使用硅基板作为基底。外延衬底包括（111）单晶Si衬底，缓冲层和晶体层。缓冲层由第一层叠单元和第二层压单元交替层叠形成。第一层压单元包括组成调制层和第一中间层。组成调制层由具有不同组成的第一单位层和第二单位层形成，以便在其中存在压缩应变。第一中间层增强了存在于组成调制层中的压缩应变。第二层压单元是基本上无应变的第二中间层。

62. 发明授权

US08410552B2 Epitaxial substrate for semiconductor device, semiconductor device, and method of manufacturing epitaxial substrate for semiconductor device 有权
标题翻译：用于半导体器件的外延衬底，半导体器件和用于半导体器件的外延衬底的制造方法
公开(公告)号：US08410552B2
公开(公告)日：2013-04-02
申请号：US12855744
申请日：2010-08-13
申请人： Makoto Miyoshi , Yoshitaka Kuraoka , Shigeaki Sumiya , Mikiya Ichimura , Tomohiko Sugiyama , Mitsuhiro Tanaka
发明人： Makoto Miyoshi , Yoshitaka Kuraoka , Shigeaki Sumiya , Mikiya Ichimura , Tomohiko Sugiyama , Mitsuhiro Tanaka
IPC分类号： H01L29/066
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/66462
摘要： Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent schottky contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of Inx1Aly1Gaz1N (x1+y1+z1=1) is formed. On the channel layer, a barrier layer formed of a second group III nitride that contains at least In and Al and has a composition of Inx2Aly2Gaz2N (x2+y2+z2=1) is formed such that an In composition ratio of a near-surface portion is smaller than an In composition ratio of a portion other than the near-surface portion.
摘要翻译：提供了能够实现具有优异的肖特基接触特性以及令人满意的器件特性的半导体器件的外延衬底。在基底基板上，形成由至少含有Al和Ga的第一III族氮化物形成的沟道层，并且具有Inx1Aly1Gaz1N（x1 + y1 + z1 = 1）的组成。在沟道层上，形成由至少包含In和Al并且具有In x2 Al y2 Ga z2 N（x2 + y2 + z2 = 1）的组成的第二III族氮化物形成的阻挡层，使得近表面的In组成比部分比除了近表面部分之外的部分的In组成比小。

63. 发明授权

US08378386B2 Epitaxial substrate for semiconductor device, semiconductor device, and method of manufacturing epitaxial substrate for semiconductor device 有权
标题翻译：用于半导体器件的外延衬底，半导体器件和用于半导体器件的外延衬底的制造方法
公开(公告)号：US08378386B2
公开(公告)日：2013-02-19
申请号：US12853716
申请日：2010-08-10
申请人： Makoto Miyoshi , Yoshitaka Kuraoka , Shigeaki Sumiya , Mikiya Ichimura , Tomohiko Sugiyama , Mitsuhiro Tanaka
发明人： Makoto Miyoshi , Yoshitaka Kuraoka , Shigeaki Sumiya , Mikiya Ichimura , Tomohiko Sugiyama , Mitsuhiro Tanaka
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/201
摘要： Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent ohmic contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of Inx1Aly1Gaz1N (x1+y1+z1=1) is formed. On the channel layer, a barrier layer formed of a second group III nitride that contains at least In and Al and has a composition of Inx2Aly2Gaz2N (x2+y2+z2=1) is formed such that an In composition ratio of a near-surface portion is larger than an In composition ratio of a portion other than the near-surface portion.
摘要翻译：提供了能够实现具有优异的欧姆接触特性以及令人满意的器件特性的半导体器件的外延衬底。在基底基板上，形成由至少含有Al和Ga的第一III族氮化物形成的沟道层，并且具有Inx1Aly1Gaz1N（x1 + y1 + z1 = 1）的组成。在沟道层上，形成由至少包含In和Al并且具有In x2 Al y2 Ga z2 N（x2 + y2 + z2 = 1）的组成的第二III族氮化物形成的阻挡层，使得近表面的In组成比部分大于除了近表面部分之外的部分的In组成比。

64. 发明授权

US08008689B2 MIS gate structure type HEMT device and method of fabricating MIS gate structure type HEMT device 失效
标题翻译： MIS门结构型HEMT器件及制造MIS栅极结构型HEMT器件的方法
公开(公告)号：US08008689B2
公开(公告)日：2011-08-30
申请号：US12185152
申请日：2008-08-04
申请人： Makoto Miyoshi , Mitsuhiro Tanaka
发明人： Makoto Miyoshi , Mitsuhiro Tanaka
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/1033 , H01L29/1066 , H01L29/2003 , H01L29/4232 , H01L29/517 , H01L29/66462
摘要： A normally-off operation type HEMT device excellent in characteristics can be realized. A two-dimensional electron gas region is formed in a periphery of a hetero-junction interface of a base layer and a barrier layer, so that access resistance in an access portion, that is, between a drain and a gate and between a gate and a source is sufficiently lowered, and at the same time, a P-type region is formed immediately under the gate. This realizes a normally-off type HEMT device having a low on-resistance. Further, when a film thickness of an insulating layer is defined as t (nm) and a relative permittivity of a substance forming the insulating layer is defined as k, a threshold voltage as high as +3 V or more can be attained by satisfying k/t≦0.85 (nm−1).
摘要翻译：能够实现特性优异的常闭型HEMT装置。二维电子气体区域形成在基底层和势垒层的异质结界面的周围，使得入射部分，即在漏极和栅极之间以及栅极和源极充分降低，同时在栅极的正下方形成P型区域。这实现了具有低导通电阻的常闭型HEMT装置。此外，当将绝缘层的膜厚定义为t（nm），并且形成绝缘层的物质的相对介电常数定义为k时，可以通过满足k（k）来获得高达+3V或更高的阈值电压 /t≦̸0.85（nm-1）。

65. 发明申请

US20110203773A1 COOLING MEMBER, MANUFACTURING METHOD AND APPARATUS THEREOF 审中-公开
标题翻译：冷却部件，制造方法及装置
公开(公告)号：US20110203773A1
公开(公告)日：2011-08-25
申请号：US13127158
申请日：2009-11-02
申请人： Junichi Teraki , Mitsuhiro Tanaka , Noriyuki Okuda
发明人： Junichi Teraki , Mitsuhiro Tanaka , Noriyuki Okuda
IPC分类号： F28D15/00 , B23P15/26
CPC分类号： H05K7/20254 , F28D15/0233 , F28D15/0275 , F28F3/12 , H01L23/473 , H01L2924/0002 , H05K7/209 , Y10T29/49359 , Y10T29/53113 , H01L2924/00
摘要： A cooling member includes a heat-transfer member having a groove and a refrigerant introducing pipe pressed into the groove. The refrigerant introducing pipe has a pressed region positioned inwardly of the edge of the heat-transfer member, and at least one curbed surface portion. A method for manufacturing a cooling member includes preparing a punch having at least one curved corner and a pressing surface, positioning the corner, and moving the punch closer to the groove to press the refrigerant introducing pipe into the groove with the pressing surface. A device for manufacturing a cooling member includes the punch and a support configured to support the heat-transfer member so the groove is positioned opposite the punch.
摘要翻译：冷却构件包括具有凹槽的传热构件和压入槽中的制冷剂引入管。制冷剂导入管具有位于传热构件的边缘的内侧的压制区域和至少一个弯曲表面部分。制造冷却构件的方法包括：制备具有至少一个弯曲角和冲压表面的冲头，定位角部，并且使冲头移动到更靠近凹槽的位置，以将压制表面压入制冷剂导入管。用于制造冷却构件的装置包括冲头和构造成支撑传热构件的支撑件，使得凹槽与冲头相对定位。

66. 发明申请

US20110024796A1 EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE 有权
标题翻译：用于半导体器件的外延衬底，半导体器件和用于生产用于半导体器件的外延衬底的工艺
公开(公告)号：US20110024796A1
公开(公告)日：2011-02-03
申请号：US12884516
申请日：2010-09-17
申请人： Makoto Miyoshi , Yoshitaka Kuraoka , Shigeaki Sumiya , Mitsuhiro Tanaka
发明人： Makoto Miyoshi , Yoshitaka Kuraoka , Shigeaki Sumiya , Mitsuhiro Tanaka
IPC分类号： H01L29/778 , H01L21/20
CPC分类号： H01L21/0262 , C30B19/00 , C30B23/02 , C30B25/02 , C30B29/403 , H01L21/0237 , H01L21/02378 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L29/2003 , H01L29/201 , H01L29/7786
摘要： Provided is an epitaxial substrate having excellent two-dimensional electron gas characteristics and reduced internal stress due to strains. A channel layer is formed of a first group III nitride represented by Inx1Aly1Gaz1N (x1+y1+z1=1) so as to have a composition in a range determined by x1=0 and 0≦y1≦0.3. A barrier layer is formed of a second group III nitride represented by Inx2Aly2Gaz2N (x2+y2+z2=1) so as to have a composition, in a ternary phase diagram with InN, AlN and GaN being vertices, in a range surrounded by five straight lines determined in accordance with the composition (AlN molar fraction) of the first group III nitride.
摘要翻译：提供了具有优异的二维电子气特性和由于应变引起的内部应力降低的外延基板。沟道层由Inx1Aly1Gaz1N（x1 + y1 + z1 = 1）表示的第一III族氮化物形成，以使得其组成在由x1 = 0和0＆lt; 1lE; y1＆nlE; 0.3确定的范围内。阻挡层由Inx2Aly2Gaz2N（x2 + y2 + z2 = 1）表示的第二III族氮化物形成，以具有以InN，AlN和GaN为顶点的三元相图中的组成，包围在五个根据第一III族氮化物的组成（AlN摩尔分数）确定的直线。

67. 发明申请

US20100289029A1 EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE 有权
标题翻译：用于半导体器件的外延衬底，半导体器件及制造用于半导体器件的外延衬底的方法
公开(公告)号：US20100289029A1
公开(公告)日：2010-11-18
申请号：US12767041
申请日：2010-04-26
申请人： Mikiya ICHIMURA , Makoto Miyoshi , Mitsuhiro Tanaka
发明人： Mikiya ICHIMURA , Makoto Miyoshi , Mitsuhiro Tanaka
IPC分类号： H01L29/20 , H01L21/784 , H01L27/12
CPC分类号： C30B25/02 , C30B19/00 , C30B23/02 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L29/2003 , H01L29/7786
摘要： An epitaxial substrate having preferable two dimensional electron gas characteristic and contact characteristic is provided in the present invention. A channel layer is formed on a base substrate with GaN. A spacer layer is formed on the channel layer with AlN. A barrier layer is formed on the spacer layer with group III nitride having a composition of InXAlyGazN (wherein x+y+z=1) and at least including In, Al, and Ga such that the composition of the barrier layer is within the range surrounded with four lines defined in accordance with the composition on a ternary phase diagram with InN, AlN, and GaN as vertexes.
摘要翻译：在本发明中提供了具有优选的二维电子气特性和接触特性的外延基板。在GaN衬底上形成沟道层。在AlN的沟道层上形成间隔层。在间隔层上形成阻挡层，其中III族氮化物具有InXAlyGazN（其中x + y + z = 1）的组成，并且至少包括In，Al和Ga，使得阻挡层的组成在用根据三元相图上的组成定义的四条线以InN，AlN和GaN为顶点包围。

68. 发明申请

US20100072493A1 ACTIVE MATRIX SUBSTRATE 有权
标题翻译：主动矩阵基板
公开(公告)号：US20100072493A1
公开(公告)日：2010-03-25
申请号：US12442870
申请日：2007-09-25
申请人： Tadayoshi Miyamoto , Mitsuhiro Tanaka
发明人： Tadayoshi Miyamoto , Mitsuhiro Tanaka
IPC分类号： H01L33/00 , H01L21/8232
CPC分类号： H01L27/124 , G02F1/136204
摘要： In an active matrix substrate (100) of the present invention, a gate bus line (105) and a gate electrode (166) extend in the first direction (the x direction). At a contact portion (168) for electrically connecting the gate bus line (105) with the drain regions of a first-conductivity-type transistor section (162) and a second-conductivity-type transistor section (164), the direction of the straight line (L1) of the shortest distance (d1) between one of a plurality of first-conductivity-type drain connecting portions (168c) that is closest to the gate bus line (105) and the gate bus line (105) is inclined with respect to the second direction (the y direction).
摘要翻译：在本发明的有源矩阵基板（100）中，栅极总线（105）和栅电极（166）沿第一方向（x方向）延伸。在用于将栅极总线（105）与第一导电型晶体管部分（162）和第二导电型晶体管部分（164）的漏极区域电连接的接触部分（168）处，与栅极总线（105）最接近的多个第一导电型漏极连接部（168c）中的一个与栅极总线（105）之间的最短距离（d1）的直线（L1）倾斜相对于第二方向（y方向）。

69. 发明授权

US07612448B2 Power module having a cooling device and semiconductor devices mounted on a resin substrate, method of producing same, and air conditioner 有权
标题翻译：具有冷却装置和安装在树脂基板上的半导体装置的功率模块，其制造方法和空调
公开(公告)号：US07612448B2
公开(公告)日：2009-11-03
申请号：US11791844
申请日：2005-12-01
申请人： Junichi Teraki , Mitsuhiro Tanaka
发明人： Junichi Teraki , Mitsuhiro Tanaka
IPC分类号： H01L31/111 , H01L25/07 , H01L25/16 , H05K1/02 , H05K7/14 , H05K7/20
CPC分类号： H01L25/072 , H01L23/3677 , H01L23/473 , H01L24/48 , H01L25/162 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H05K1/0206 , H05K1/021 , H05K1/0272 , H05K1/0298 , H05K1/183 , H05K3/0061 , H05K7/20927 , H05K2201/064 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A power module includes a power semiconductor, a non-power semiconductor, one resin substrate, and a cooling device. The power semiconductor and the non-power semiconductor configure a power supply circuit for performing power conversion. Both the power semiconductor and the non-power semiconductor are mounted on the resin substrate. The cooling device is disposed in order to cool the power semiconductor.
摘要翻译：功率模块包括功率半导体，非功率半导体，一个树脂基板和冷却装置。功率半导体和非功率半导体构成用于进行电力转换的电源电路。功率半导体和非功率半导体都安装在树脂基板上。设置冷却装置以冷却功率半导体。

70. 发明申请

US20090050938A1 MIS GATE STRUCTURE TYPE HEMT DEVICE AND METHOD OF FABRICATING MIS GATE STRUCTURE TYPE HEMT DEVICE 失效
标题翻译：门控结构类型HEMT器件和制造MIS门结构类型HEMT器件的方法
公开(公告)号：US20090050938A1
公开(公告)日：2009-02-26
申请号：US12185152
申请日：2008-08-04
申请人： Makoto Miyoshi , Mitsuhiro Tanaka
发明人： Makoto Miyoshi , Mitsuhiro Tanaka
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/7787 , H01L29/1033 , H01L29/1066 , H01L29/2003 , H01L29/4232 , H01L29/517 , H01L29/66462
摘要： A normally-off operation type HEMT device excellent in characteristics can be realized. A two-dimensional electron gas region is formed in a periphery of a hetero-junction interface of a base layer and a barrier layer, so that access resistance in an access portion, that is, between a drain and a gate and between a gate and a source is sufficiently lowered, and at the same time, a P-type region is formed immediately under the gate. This realizes a normally-off type HEMT device having a low on-resistance. Further, when a film thickness of an insulating layer is defined as t (nm) and a relative permittivity of a substance forming the insulating layer is defined as k, a threshold voltage as high as +3 V or more can be attained by satisfying k/t≦0.85 (nm−1).
摘要翻译：能够实现特性优异的常闭型HEMT装置。二维电子气体区域形成在基底层和势垒层的异质结界面的周围，使得入射部分，即在漏极和栅极之间以及栅极和源极充分降低，同时在栅极的正下方形成P型区域。这实现了具有低导通电阻的常闭型HEMT装置。此外，当将绝缘层的膜厚定义为t（nm），并且形成绝缘层的物质的相对介电常数定义为k时，可以通过满足k值来获得高达+3V或更高的阈值电压 /t<=0.85（nm-1）。

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