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61. 发明授权

US07751217B2 Content addressable memory using phase change devices 有权
标题翻译：内容可寻址内存使用相变设备
公开(公告)号：US07751217B2
公开(公告)日：2010-07-06
申请号：US12166311
申请日：2008-07-01
申请人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
发明人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C13/0004 , G11C15/046
摘要： Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device.
摘要翻译：使用相变装置的内容寻址存储装置。内容可寻址存储器件的一个方面是使用相对较低功率的搜索线访问元件和相对较高功率的字线访问元件。字线访问元件仅在写入操作期间使用，并且搜索线访问元件仅在搜索操作期间被使用。字线访问元件电耦合到相变存储器元件的第二端和字线。搜索线访问元件还电耦合到相变存储元件的第二端和搜索线。搜索线电耦合到匹配线。位线电耦合到相变存储元件的第一端。此外，内容可寻址存储器件中还包括互补的一组存取元件，互补相变存储器元件，互补搜索线和互补位线。

62. 发明授权

US07944740B2 Multi-level cell programming of PCM by varying the reset amplitude 失效
标题翻译：通过改变复位幅度对PCM进行多级单元编程
公开(公告)号：US07944740B2
公开(公告)日：2011-05-17
申请号：US12564904
申请日：2009-09-22
申请人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
发明人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.
摘要翻译：相变存储器件及其编程方法。该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。该方法包括确定用于相变存储器件的特征化的RESET电流斜率。该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

63. 发明授权

US07881089B2 Coding techniques for improving the sense margin in content addressable memories 有权
标题翻译：用于改善内容可寻址存储器中的检测边缘的编码技术
公开(公告)号：US07881089B2
公开(公告)日：2011-02-01
申请号：US12392049
申请日：2009-02-24
申请人： Michele M. Franceschini , Chung H. Lam , Luis A. Lastras , Bipin Rajendran
发明人： Michele M. Franceschini , Chung H. Lam , Luis A. Lastras , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C7/1006 , G11C13/0004 , G11C15/02 , G11C15/046
摘要： A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word.
摘要翻译：使用编码数据字和搜索词的内容可寻址存储器，以及用于操作这样的设备的技术。在一个实施例中，当数据字与搜索词不匹配时，数据字被转换成保证在存储器搜索操作期间不同二进制值的至少两个码字位的失配的码字。在另一个实施例中，搜索词被变换成搜索码，使得当数据字和搜索词之间存在至少一个比特的不匹配时，码字和搜索码之间的汉明距离大于给定阈值。

64. 发明申请

US20100265748A1 HIGH DENSITY TERNARY CONTENT ADDRESSABLE MEMORY 有权
标题翻译：高密度内容可寻址存储器
公开(公告)号：US20100265748A1
公开(公告)日：2010-10-21
申请号：US12427484
申请日：2009-04-21
申请人： Chung H. Lam , Bipin Rajendran
发明人： Chung H. Lam , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C11/56
CPC分类号： G11C15/046 , G11C11/5678 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing data words. Each data bit in the data words is set to one of three values of a first binary value, a second binary value, and a don't care value. An aspect of the content addressable memory device is the use of a single memory element and an access device in the memory cells. The memory cells are arranged such that each memory cell is electrically coupled to a single bit line, a single match line, and a single word line. The memory elements in the memory cells store low resistance states if the data bit value is the first binary value, high resistance states if the data bit value is the second binary value, and very high resistance states if the data bit value is the don't care value.
摘要翻译：一种具有存储数据字的多个存储器单元的内容可寻址存储器件。数据字中的每个数据位被设置为第一二进制值，第二二进制值和不关心值的三个值之一。内容可寻址存储器件的一个方面是在存储器单元中使用单个存储器元件和存取器件。存储器单元被布置成使得每个存储器单元电耦合到单个位线，单个匹配线和单个字线。如果数据位值是第一个二进制值，则存储器单元中的存储元件存储低电阻状态，如果数据位值是第二个二进制值则为高电阻状态，如果数据位值为“ 关心价值。

65. 发明申请

US20100214811A1 CODING TECHNIQUES FOR IMPROVING THE SENSE MARGIN IN CONTENT ADDRESSABLE MEMORIES 有权
标题翻译：用于改善内容可寻址存储器中的感应信号的编码技术
公开(公告)号：US20100214811A1
公开(公告)日：2010-08-26
申请号：US12392049
申请日：2009-02-24
申请人： Michele M. Franceschini , Chung H. Lam , Luis A. Lastras , Bipin Rajendran
发明人： Michele M. Franceschini , Chung H. Lam , Luis A. Lastras , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C7/1006 , G11C13/0004 , G11C15/02 , G11C15/046
摘要： A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word.
摘要翻译：使用编码数据字和搜索词的内容可寻址存储器，以及用于操作这样的设备的技术。在一个实施例中，当数据字与搜索词不匹配时，数据字被转换成保证在存储器搜索操作期间不同二进制值的至少两个码字位的失配的码字。在另一个实施例中，搜索词被变换成搜索码，使得当数据字和搜索词之间存在至少一个比特的不匹配时，码字和搜索码之间的汉明距离大于给定阈值。

66. 发明授权

US07606067B2 Method to create a uniformly distributed multi-level cell (MLC) bitstream from a non-uniform MLC bitstream 失效
标题翻译：从非均匀MLC比特流创建均匀分布的多级单元（MLC）比特流的方法
公开(公告)号：US07606067B2
公开(公告)日：2009-10-20
申请号：US11774539
申请日：2007-07-06
申请人： Chung H. Lam , Bipin Rajendran
发明人： Chung H. Lam , Bipin Rajendran
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C11/5628 , G11C16/3418 , G11C29/00
摘要： A method, system, and computer software product for operating a collection of memory cells. Each memory cell in the collection of memory cells is configured to store a binary multi-bit value delimited by characteristic parameter bands. In one embodiment, a transforming unit transforms an original collection of data to a transformed collection of data using a reversible mathematical operator. The original collection of data has binary multi-bit values arbitrarily distributed across the binary multi-bit values assigned to the characteristic parameter bands and the transformed collection of data has binary multi-bit values substantially uniformly distributed across the binary multi-bit values assigned to the characteristic parameter bands.
摘要翻译：一种用于操作存储器单元集合的方法，系统和计算机软件产品。存储器单元集合中的每个存储器单元被配置为存储由特征参数带限定的二进制多位值。在一个实施例中，变换单元使用可逆数学运算符将原始数据集合转换成变换的数据集合。原始数据集合具有任意分配给分配给特征参数带的二进制多位值的二进制多位值，并且变换的数据集合具有基本上均匀分布在分配给二进制多位值的二进制多位值的二进制多位值特征参数带。

67. 发明授权

US08558210B2 Polysilicon emitter BJT access device for PCRAM 有权
标题翻译：用于PCRAM的多晶硅发射体BJT接入装置
公开(公告)号：US08558210B2
公开(公告)日：2013-10-15
申请号：US13449378
申请日：2012-04-18
申请人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
发明人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/0623 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.
摘要翻译：具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。间隔层包含在绝缘区域内。

68. 发明申请

US20120199806A1 POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM 有权
标题翻译：用于PCRAM的多晶硅发射器BJT接入装置
公开(公告)号：US20120199806A1
公开(公告)日：2012-08-09
申请号：US13449378
申请日：2012-04-18
申请人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
发明人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
IPC分类号： H01L47/00
CPC分类号： H01L45/148 , H01L27/0623 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.
摘要翻译：具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。间隔层包含在绝缘区域内。

69. 发明申请

US20100226161A1 TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES 有权
标题翻译：使用相位变更设备的内容可寻址存储器
公开(公告)号：US20100226161A1
公开(公告)日：2010-09-09
申请号：US12399346
申请日：2009-03-06
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C11/56
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

70. 发明授权

US09269042B2 Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices 有权
标题翻译：使用相变突触装置在神经元网络中产生尖峰时间依赖性可塑性
公开(公告)号：US09269042B2
公开(公告)日：2016-02-23
申请号：US12895791
申请日：2010-09-30
申请人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04 , G11C11/54 , G11C13/00
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
摘要翻译：本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

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