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61. 发明授权

US08171477B2 Method and system for performing real-time operation 有权
标题翻译：执行实时操作的方法和系统
公开(公告)号：US08171477B2
公开(公告)日：2012-05-01
申请号：US12172285
申请日：2008-07-14
申请人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii , Hirokuni Yano
发明人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii , Hirokuni Yano
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/5066
摘要： An information processing system performs a real-time operation including a combination of a plurality of tasks. The system includes a plurality of processors, a unit which stores structural description information and a plurality of programs describing procedures corresponding to the tasks, the structural description information indicating a relationship in input/output between the programs and including cost information concerning time required for executing each of the programs, a unit which determines an execution start timing and execution term of each of a plurality of threads for execution of the programs based on the structural description information, and a unit which performs a scheduling operation of assigning the threads to at least one of the processors according to a result of the determining.
摘要翻译：信息处理系统执行包括多个任务的组合的实时操作。该系统包括多个处理器，存储结构描述信息的单元和描述与任务相对应的过程的多个程序，表示程序之间的输入/输出中的关系的结构性描述信息，并且包括关于执行所需时间的成本信息每个程序，基于结构描述信息确定用于执行程序的多个线程中的每一个的执行开始时间和执行项的单元，以及执行将线程分配至少的调度操作的单元根据确定的结果，处理器中的一个。

62. 发明授权

US08060925B2 Processor, memory, computer system, and method of authentication 有权
标题翻译：处理器，内存，计算机系统和验证方法
公开(公告)号：US08060925B2
公开(公告)日：2011-11-15
申请号：US11508935
申请日：2006-08-24
申请人： Kenichiro Yoshii , Tatsunori Kanai
发明人： Kenichiro Yoshii , Tatsunori Kanai
IPC分类号： G06F15/16
CPC分类号： G06F12/1466 , G06F21/445 , G06F21/57 , G06F2221/2129
摘要： A processor communicating with a first memory configured to store first information and first data, and communicating with a second memory configured to store second information and second data, includes a computing unit configured to perform computation using the first data and the second data; an storing unit configured integrally with the computing unit to store first authentication information and second authentication information; a reading unit configured to read out the first information and the second information; an authenticating unit configured to authenticate the first memory by comparing the first information and the first authentication information, and to authenticate the second memory by comparing the second information and the second authentication information; and an controlling unit configured to control an access of the computing unit to the first memory and the second memory based on a result of the authentications.
摘要翻译：与被配置为存储第一信息和第一数据的第一存储器通信并与被配置为存储第二信息和第二数据的第二存储器通信的处理器包括被配置为使用第一数据和第二数据执行计算的计算单元; 存储单元，与所述计算单元一体地配置以存储第一认证信息和第二认证信息; 读取单元，被配置为读出第一信息和第二信息; 认证单元，被配置为通过比较第一信息和第一认证信息来认证第一存储器，并且通过比较第二信息和第二认证信息来认证第二存储器; 以及控制单元，被配置为基于所述认证的结果来控制所述计算单元对所述第一存储器和所述第二存储器的访问。

63. 发明授权

US08006272B2 Method and apparatus of displaying bit stream data, method and apparatus for generating bit stream data, and storage medium 失效
标题翻译：显示比特流数据的方法和装置，用于产生比特流数据的方法和装置以及存储介质
公开(公告)号：US08006272B2
公开(公告)日：2011-08-23
申请号：US12041329
申请日：2008-03-03
申请人： Toru Kambayashi , Tatsunori Kanai , Takeshi Saito , Hiroshi Yao , Shigeyasu Natsubori , Osamu Hori , Toshimitsu Kaneko , Toshihiro Morohoshi , Takahiro Harashima , Yoshinori Suzuki , Shigeru Oyanagi , Takeshi Aikawa
发明人： Toru Kambayashi , Tatsunori Kanai , Takeshi Saito , Hiroshi Yao , Shigeyasu Natsubori , Osamu Hori , Toshimitsu Kaneko , Toshihiro Morohoshi , Takahiro Harashima , Yoshinori Suzuki , Shigeru Oyanagi , Takeshi Aikawa
IPC分类号： H04N7/20 , H04N7/16
CPC分类号： H04N21/262 , G06Q20/3678 , H04N5/4401 , H04N5/445 , H04N21/235 , H04N21/4305 , H04N21/4331 , H04N21/4334 , H04N21/4335 , H04N21/4348 , H04N21/435 , H04N21/4622 , H04N21/478 , H04N21/8166
摘要： According to a data display method, data having a program unit and instruction data for the program unit multiplexed on bit stream data is received. The program unit is extracted from the received data and is stored in a memory. The instruction data is extracted from the received data, and the program unit or part thereof specified by the instruction data is read from the memory and is executed. Then, the bit stream data and the execution result are displayed. This ensures smooth synchronization of reproduction of a bit stream with execution of an associated program and efficient use of resources.
摘要翻译：根据数据显示方法，接收具有程序单元的数据和用于在比特流数据上复用的程序单元的指令数据。从接收到的数据中提取程序单元并将其存储在存储器中。从接收的数据中提取指令数据，并且从存储器读取由指令数据指定的程序单元或其一部分，并执行。然后，显示比特流数据和执行结果。这确保了位流的再现与相关程序的执行和资源的有效利用的顺利同步。

64. 发明授权

US07971014B2 Information processing apparatus and data recovering method 失效
标题翻译：信息处理装置和数据恢复方法
公开(公告)号：US07971014B2
公开(公告)日：2011-06-28
申请号：US12198473
申请日：2008-08-26
申请人： Kenichiro Yoshii , Hiroshi Yao , Tomohide Jokan , Tatsunori Kanai
发明人： Kenichiro Yoshii , Hiroshi Yao , Tomohide Jokan , Tatsunori Kanai
IPC分类号： G06F12/16 , G06F13/00
CPC分类号： G06F11/1441 , G06F11/141
摘要： In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address.
摘要翻译：在信息处理装置中，当发出写入非易失性的主存储单元的存储内容的指令时，从备份中提取包含在具有读取许可的设置的备份数据中的数据和写入目的地地址存储在非易失性的备份存储单元中的数据。此外，根据从备份数据提取的数据和写入目的地地址，将数据写入由写入目的地址指示的主存储单元的存储区域。

65. 发明授权

US07761779B2 Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method 失效
标题翻译：访问控制装置，访问控制系统，处理器，访问控制方法，存储器访问控制装置，存储器访问控制系统和存储器访问控制方法
公开(公告)号：US07761779B2
公开(公告)日：2010-07-20
申请号：US11519797
申请日：2006-09-13
申请人： Tatsunori Kanai , Kenichiro Yoshii
发明人： Tatsunori Kanai , Kenichiro Yoshii
IPC分类号： G06F12/14
CPC分类号： G06F11/1032
摘要： An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.
摘要翻译：访问控制装置包括奇偶校验生成器，其生成要写入存储器的原始数据的奇偶校验; 以及奇偶校验加法器，通过将奇偶校验与原始数据相加来生成奇偶校验相加数据; 第一校正子发生器，其产生第一掩模数据的第一校正子，以掩蔽所述奇偶校验相加数据。第一个综合征是与写入器访问存储器时要使用的第一访问代码预先相关联的值。该装置还包括：第一掩模发生器，其基于第一综合征，第一访问码和第一存储器地址生成第一掩模数据; 第一XOR单元，通过计算奇偶校验相加数据和第一掩码数据之间的异或来获得第一后操作数据; 以及将第一操作后数据写入存储器的写入单元。

66. 发明授权

US07743208B2 Storage apparatus and area allocation method 失效
标题翻译：存储设备和区域分配方法
公开(公告)号：US07743208B2
公开(公告)日：2010-06-22
申请号：US11797286
申请日：2007-05-02
申请人： Hideki Yoshida , Tatsunori Kanai , Nobuo Sakiyama
发明人： Hideki Yoshida , Tatsunori Kanai , Nobuo Sakiyama
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F3/0641 , G06F3/0613 , G06F3/0617 , G06F3/067 , G06F11/2094 , G06F17/3015 , H04L69/329
摘要： A file memory stores data corresponding to identifiers of an allocated area in an identifier space. A first memory stores a basis position of the allocated area in the identifier space. A second memory stores a weight of the storage apparatus as a performance degree. A first decision unit decides a space width to divisionally allocate the identifier space with another storage apparatus by using the weight and a weight of another storage apparatus. Another storage apparatus allocates a neighboring area of the allocated area in the identifier space. A second decision unit decides the allocated area of an area between the basis position and a basis position of the neighboring area in the identifier space by using the space width.
摘要翻译：文件存储器将对应于分配区域的标识符的数据存储在标识符空间中。第一存储器将分配的区域的基准位置存储在标识符空间中。第二存储器将存储装置的重量作为性能程度存储。第一决定单元通过使用另一存储装置的权重和权重来决定空间宽度以与另一存储装置分开分配标识符空间。另一个存储装置在所述标识符空间中分配所分配区域的相邻区域。第二判定单元通过使用空格宽度来确定标识符空间中的基准位置与相邻区域的基准位置之间的区域的分配面积。

67. 发明授权

US07653861B2 Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method 失效
标题翻译：访问控制装置，访问控制系统，处理器，访问控制方法，存储器访问控制装置，存储器访问控制系统和存储器访问控制方法
公开(公告)号：US07653861B2
公开(公告)日：2010-01-26
申请号：US11523003
申请日：2006-09-19
申请人： Tatsunori Kanai , Kenichiro Yoshii
发明人： Tatsunori Kanai , Kenichiro Yoshii
IPC分类号： H03M13/00
CPC分类号： G06F12/1466 , G06F11/1016 , G06F12/1408 , G06F21/79
摘要： An access control apparatus includes a writer syndrome generator that generates a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when a writer that requests writing of the write data in the memory accesses the memory; a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data; and a write address converter that converts the write address into another address determined by the writer access ID.
摘要翻译：一种访问控制装置，包括：写入器校验发生器，其生成写入器掩码数据的写入器校验器以掩蔽奇偶校验相加数据;写入器校验器与写入器访问ID相关联，当写入器请求写入数据到存储器中时访问内存写入掩码生成器，其基于写入器综合符，写入器访问ID和写入器写入写入数据的存储器中的写入地址生成写入器掩模数据; 第一XOR计算器，通过计算奇偶校验相加数据和写入器掩码数据之间的异或来获得第一后操作数据; 以及将写入地址转换成由写入器访问ID确定的另一地址的写入地址转换器。

68. 发明申请

US20090164743A1 INFORMATION PROCESSING APPARATUS AND DATA RECOVERING METHOD 有权
标题翻译：信息处理装置和数据恢复方法
公开(公告)号：US20090164743A1
公开(公告)日：2009-06-25
申请号：US12199111
申请日：2008-08-27
申请人： Kenichiro YOSHII , Hiroshi Yao , Tomohide Jokan , Tatsunori Kanai
发明人： Kenichiro YOSHII , Hiroshi Yao , Tomohide Jokan , Tatsunori Kanai
IPC分类号： G06F12/16 , G06F13/00
CPC分类号： G06F11/1441 , G06F1/30
摘要： A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.
摘要翻译：信息处理装置包括：在上一次修改时，指示将存储的主存储单元的存储内容写入主存储单元的存储内容中的顺序号，用于识别是否回写到主存储器单元从存储在备用存储器单元中的备份数据需要存储在序列号存储单元中的序列号。信息处理装置选择包括表示完全进行写入的完整性验证数据的备份数据。信息处理装置提取包含在选择的备份数据中的原始数据和写入目的地地址，并将原始数据和从备份数据提取的写入地址的原始数据写入主存储器单元的存储区域，由写入目标地址指示。

69. 发明授权

US07356666B2 Local memory management system with plural processors 有权
标题翻译：具有多个处理器的本地存储器管理系统
公开(公告)号：US07356666B2
公开(公告)日：2008-04-08
申请号：US10808320
申请日：2004-03-25
申请人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii
发明人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii
IPC分类号： G06F12/00
CPC分类号： G06F9/544 , G06F9/5016
摘要： An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third local memories in part of an effective address space of a first thread to be executed by the first processor. The mapped one of the second and third local memories is the local memory of a corresponding one of the second and third processors, which executes a second thread interacting with the first thread. The system also includes a unit that changes a local memory to be mapped in part of the effective address space of the first thread from the one of the second and third local memories to the other.
摘要翻译：信息处理系统包括具有第一本地存储器的第一处理器，具有第二本地存储器的第二处理器和具有第三本地存储器的第三处理器。该系统还包括一个单元，其将第一和第三本地存储器之一映射到要由第一处理器执行的第一线程的有效地址空间的一部分。第二和第三本地存储器中映射的一个是第二和第三处理器中对应的一个处理器的本地存储器，其执行与第一线程交互的第二线程。该系统还包括将本地存储器改变为将第一线程的有效地址空间的一部分映射到第二和第三本地存储器之一的单元。

70. 发明申请

US20070136647A1 Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method 失效
标题翻译：访问控制装置，访问控制系统，处理器，访问控制方法，存储器访问控制装置，存储器访问控制系统和存储器访问控制方法
公开(公告)号：US20070136647A1
公开(公告)日：2007-06-14
申请号：US11519797
申请日：2006-09-13
申请人： Tatsunori Kanai , Kenichiro Yoshii
发明人： Tatsunori Kanai , Kenichiro Yoshii
IPC分类号： H03M13/00
CPC分类号： G06F11/1032
摘要： An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.
摘要翻译：访问控制装置包括奇偶校验生成器，其生成要写入存储器的原始数据的奇偶校验; 以及奇偶校验加法器，通过将奇偶校验与原始数据相加来生成奇偶校验相加数据; 第一校正子发生器，其产生第一掩模数据的第一校正子，以掩蔽所述奇偶校验相加数据。第一个综合征是与写入器访问存储器时要使用的第一访问代码预先相关联的值。该装置还包括：第一掩模发生器，其基于第一综合征，第一访问码和第一存储器地址生成第一掩模数据; 第一XOR单元，通过计算奇偶校验相加数据和第一掩码数据之间的异或来获得第一后操作数据; 以及将第一操作后数据写入存储器的写入单元。

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