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61. 发明授权

US08543966B2 Test path selection and test program generation for performance testing integrated circuit chips 有权
标题翻译：测试路径选择和测试程序生成用于性能测试集成电路芯片
公开(公告)号：US08543966B2
公开(公告)日：2013-09-24
申请号：US13294210
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.
摘要翻译：一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径。

62. 发明申请

US20130226536A1 DYNAMICALLY DETERMINING NUMBER OF SIMULATIONS REQUIRED FOR CHARACTERIZING INTRA-CIRCUIT INCONGRUENT VARIATIONS 有权
标题翻译：动态确定表征电路内容变化所需的模拟数量
公开(公告)号：US20130226536A1
公开(公告)日：2013-08-29
申请号：US13406897
申请日：2012-02-28
申请人： Peter A. Habitz , Amol A. Joshi , Amith Singhee , James E. Sundquist , Wangyang Zhang
发明人： Peter A. Habitz , Amol A. Joshi , Amith Singhee , James E. Sundquist , Wangyang Zhang
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F17/50 , G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.
摘要翻译：公开了一种方法，其包括使用在计算机化设备上运行的电路识别引擎来检测集成电路中的数量和类型设备。该方法通过选择一组主导有源器件并使用该主导有源器件集来执行仿真来表征器件变化。可以使用三种不同的选项来优化任何电弧/压摆/负载组合的模拟次数。积极减少使用最少数量的模拟，以牺牲一些精度损失为代价，保守的减少可以减少精确度损失可忽略的模拟次数，动态减少动态地确定给定精度要求所需的最小模拟次数。

63. 发明授权

US08490040B2 Disposition of integrated circuits using performance sort ring oscillator and performance path testing 有权
标题翻译：使用性能分类环形振荡器和性能路径测试对集成电路进行处理
公开(公告)号：US08490040B2
公开(公告)日：2013-07-16
申请号：US13294220
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译：一种配置集成电路芯片的方法和系统。该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。

64. 发明申请

US20130125073A1 TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS 有权
标题翻译：性能测试集成电路卡的测试路径选择和测试程序生成
公开(公告)号：US20130125073A1
公开(公告)日：2013-05-16
申请号：US13294210
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths
摘要翻译：一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径

65. 发明申请

US20110126163A1 METHOD TO REDUCE DELAY VARIATION BY SENSITIVITY CANCELLATION 失效
标题翻译：通过灵敏度消除来减少延迟变化的方法
公开(公告)号：US20110126163A1
公开(公告)日：2011-05-26
申请号：US12625139
申请日：2009-11-24
申请人： Peter A. Habitz , Eric A. Foreman , Gustavo E. Tellez
发明人： Peter A. Habitz , Eric A. Foreman , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/12 , G06F2217/84 , Y02P90/265
摘要： A method receives an initial circuit design. The circuit design includes at least one path having at least one beginning point comprising a source, at least one ending point comprising a sink, and one or more circuit elements between the source and the sink. The method evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements. Further, the method alters the elements within the path until elements that produce positive changes to the timing performance parameter for a given manufacturing variable change approximately equals (in magnitude) elements that produce negative changes to the timing performance parameter for the given manufacturing variable change, to produce an altered circuit design.
摘要翻译：一种方法接收初始电路设计。该电路设计包括至少一个路径，该至少一个路径具有包括源的至少一个起始点，包括宿的至少一个终点以及源和宿之间的一个或多个电路元件。该方法评估每个元件的制造变化的时序性能参数灵敏度，以识别每个元件将增加或减少与制造元件相关联的每个制造变量中的每个变化的路径的时序性能参数。此外，该方法改变路径内的元素，直到产生对于给定制造变量的定时性能参数的正变化的元素大致等于（在大小上）元素，该元素对于给定的制造变量变化而对定时性能参数产生负变化，以产生改变的电路设计。

66. 发明申请

US20110055793A1 TIMING CLOSURE ON MULTIPLE SELECTIVE CORNERS IN A SINGLE STATISTICAL TIMING RUN 有权
标题翻译：在单个统计时序运行中多个选择角的定时关闭
公开(公告)号：US20110055793A1
公开(公告)日：2011-03-03
申请号：US12549061
申请日：2009-08-27
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Susan K. Lichtensteiger , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Susan K. Lichtensteiger , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks.
摘要翻译：描述了在单个统计时序运行中覆盖多个选择性定时角的方法。在一个实施例中，在涵盖无限制过程参数/环境条件的完整参数空间上运行单个统计时序分析。统计时间分析的结果预计为所选角。在具有最差松弛度的角落上进行定时关闭。

67. 发明申请

US20100318951A1 SYSTEM AND METHOD FOR DEVICE HISTORY BASED DELAY VARIATION ADJUSTMENT DURING STATIC TIMING ANALYSIS 有权
标题翻译：基于静态时序分析的基于设备历史的延迟变化调整系统与方法
公开(公告)号：US20100318951A1
公开(公告)日：2010-12-16
申请号：US12484293
申请日：2009-06-15
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.
摘要翻译：一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个基于历史的延迟变异性和时间传播。

68. 发明申请

US20100293512A1 CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT 有权
标题翻译：芯片设计和优化方法优化
公开(公告)号：US20100293512A1
公开(公告)日：2010-11-18
申请号：US12467326
申请日：2009-05-18
申请人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
发明人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031
摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.
摘要翻译：公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。基于JPD，生成相应的收益率曲线。利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以产生利润模型。基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力。

69. 发明授权

US07823115B2 Method of generating wiring routes with matching delay in the presence of process variation 有权
标题翻译：在存在过程变化的情况下生成具有匹配延迟的布线路线的方法
公开(公告)号：US07823115B2
公开(公告)日：2010-10-26
申请号：US12108629
申请日：2008-04-24
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

70. 发明授权

US07620921B2 IC chip at-functional-speed testing with process coverage evaluation 有权
标题翻译： IC芯片在功能速度测试与过程覆盖评估
公开(公告)号：US07620921B2
公开(公告)日：2009-11-17
申请号：US11741164
申请日：2007-04-27
申请人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
摘要翻译：公开了用于评估IC芯片的方法，系统和程序产品。在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。

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