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61. 发明申请

US20060123218A1 System and method for assigning tags to control instruction processing in a superscalar processor 失效
公开(公告)号：US20060123218A1
公开(公告)日：2006-06-08
申请号：US11338817
申请日：2006-01-25
申请人： Kevin Iadonato , Trevor Deosaran , Sanjiv Garg
发明人： Kevin Iadonato , Trevor Deosaran , Sanjiv Garg
IPC分类号： G06F15/00
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for tagging the instructions. The tags are arranged in the queue in an order specified by the program order of their corresponding instructions. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file stores an instruction's information at a location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.

62. 发明申请

US20060020773A1 System and method for register renaming 失效
公开(公告)号：US20060020773A1
公开(公告)日：2006-01-26
申请号：US11235090
申请日：2005-09-27
申请人： Trevor Deosaran , Sanjiv Garg , Kevin Iadonato
发明人： Trevor Deosaran , Sanjiv Garg , Kevin Iadonato
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.

63. 发明授权

US5892963A System and method for assigning tags to instructions to control instruction execution 失效
标题翻译：将标签分配给用于控制指令执行的指令的系统和方法
公开(公告)号：US5892963A
公开(公告)日：1999-04-06
申请号：US799462
申请日：1997-02-13
申请人： Kevin Ray Iadonato , Trevor Anthony Deosaran , Sanjiv Garg
发明人： Kevin Ray Iadonato , Trevor Anthony Deosaran , Sanjiv Garg
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3857 , G06F9/3885
摘要： Tag monitoring system for assigning tags to instructions. A memory unit stores instructions to be executed by an execution unit. Before execution an instruction fetch unit decodes the instructions. A register file stores the decoded instructions. A queue having a plurality of slots containing tags which are used for tagging the decoded instructions. A control unit assigns the tags to decoded instructions, monitors the completion of executed instructions, and advances the tags in the queue upon completion of an executed instruction. The register stores a given decoded instruction at an address location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, a a decoded instruction is read out of a read output port enabled by the tag assigned to that decoded instruction in program order.
摘要翻译：标签监控系统，用于将标签分配给指令。存储单元存储由执行单元执行的指令。执行前，指令取出单元解码指令。寄存器文件存储解码的指令。具有包含用于标记解码指令的标签的多个时隙的队列。控制单元将标签分配给经解码的指令，监视执行指令的完成，并且在完成执行指令时将标签推进队列中。寄存器在由分配给该指令的标签定义的寄存器文件的地址位置处存储给定的解码指令。寄存器文件还包含多个读取地址使能端口和对应的读取输出端口。来自队列的每个时隙被耦合到对应的一个读取地址使能端口。因此，从由分配给该解码指令的标签启用的读取输出端口以编程顺序读出解码指令。

64. 发明授权

US5590295A System and method for register renaming 失效
公开(公告)号：US5590295A
公开(公告)日：1996-12-31
申请号：US478531
申请日：1995-06-07
申请人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
发明人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.

65. 发明授权

US5493687A RISC microprocessor architecture implementing multiple typed register sets 失效
公开(公告)号：US5493687A
公开(公告)日：1996-02-20
申请号：US726773
申请日：1991-07-08
申请人： Sanjiv Garg , Derek J. Lentz , Le T. Nguyen , Sho L. Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le T. Nguyen , Sho L. Chen
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30181 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

66. 发明授权

US07979678B2 System and method for register renaming 失效
标题翻译：用于注册重命名的系统和方法
公开(公告)号：US07979678B2
公开(公告)日：2011-07-12
申请号：US12472052
申请日：2009-05-26
申请人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
发明人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
IPC分类号： G06F9/38
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.
摘要翻译：一种用于在具有用于存储要由处理器执行的指令组的可变提前指令窗口的处理器中执行寄存器重命名源寄存器的系统和方法，其中当位置变得可用时将新指令添加到可变提前指令窗口。标签被分配给变量提前指令窗口中的每个指令。离开窗口的每个指令的标签被分配给要添加到其中的下一个新指令。由处理器执行的指令的结果根据其相应的标签存储在临时缓冲器中，以避免输出和反依赖。因此，临时缓冲器允许处理器按顺序并行执行指令。仅对添加到变量提前指令窗口的每个新指令执行输入相关性的数据依赖性检查，并执行寄存器重命名以避免输入依赖关系。

67. 发明授权

US07685402B2 RISC microprocessor architecture implementing multiple typed register sets 失效
标题翻译： RISC微处理器架构实现多种类型的寄存器集
公开(公告)号：US07685402B2
公开(公告)日：2010-03-23
申请号：US11651009
申请日：2007-01-09
申请人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
IPC分类号： G06F15/00
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30189 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.
摘要翻译：一种用于以多种模式操作的数据处理器的寄存器系统。寄存器系统提供多个相同的寄存器组，数据处理器控制访问，使得指令和过程不需要指定任何给定的存储体。整数寄存器集包括第一（RA [23：0]）和第二（RA [31:24]）子集和影子子集（RT [31:24]）。当数据处理器处于第一模式时，指令访问第一和第二子集。当数据处理器处于第二模式时，指令可以访问第一子集，但是任何访问第二子集的尝试都被重新路由到阴影子集，而不是透明地指向该指令，从而允许系统例程看起来使用第二子集，而没有必须保存和恢复哪个用户例程已写入第二个子集的数据。重分类寄存器组分别提供整数宽度数据和浮点宽度数据，以响应整数指令和浮点指令。布尔比较指令为要比较的源数据指定特定的整数或浮点寄存器，并为结果指定一个特定的布尔寄存器，因此没有专用的固定位置状态标志。布尔组合指令组合指定的布尔寄存器，用于执行复杂的布尔比较而无需干预条件分支指令，以最大限度地减少管道中断。

68. 发明授权

US07555631B2 RISC microprocessor architecture implementing multiple typed register sets 失效
标题翻译： RISC微处理器架构实现多种类型的寄存器集
公开(公告)号：US07555631B2
公开(公告)日：2009-06-30
申请号：US10060086
申请日：2002-01-31
申请人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le Trong Nguyen , Sho Long Chen
IPC分类号： G06F15/00
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30189 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.
摘要翻译：一种用于以多种模式操作的数据处理器的寄存器系统。寄存器系统提供多个相同的寄存器组，数据处理器控制访问，使得指令和过程不需要指定任何给定的存储体。整数寄存器集包括第一（RA [23：0]）和第二（RA [31:24]）子集和影子子集（RT [31:24]）。当数据处理器处于第一模式时，指令访问第一和第二子集。当数据处理器处于第二模式时，指令可以访问第一子集，但是任何访问第二子集的尝试都被重新路由到阴影子集，而不是透明地指向该指令，从而允许系统例程看起来使用第二子集，而没有必须保存和恢复哪个用户例程已写入第二个子集的数据。重分类寄存器组分别提供整数宽度数据和浮点宽度数据，以响应整数指令和浮点指令。布尔比较指令为要比较的源数据指定特定的整数或浮点寄存器，并为结果指定一个特定的布尔寄存器，因此没有专用的固定位置状态标志。布尔组合指令组合指定的布尔寄存器，用于执行复杂的布尔比较而无需干预条件分支指令，以最大限度地减少管道中断。

69. 发明申请

US20090013158A1 System and Method for Assigning Tags to Control Instruction Processing in a Superscalar Processor 失效
标题翻译：用于分配标签以控制超标量处理器中的指令处理的系统和方法
公开(公告)号：US20090013158A1
公开(公告)日：2009-01-08
申请号：US12210738
申请日：2008-09-15
申请人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
发明人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
IPC分类号： G06F9/30
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A tag monitoring system for assigning tags to instructions embodied in software on a tangible computer-readable storage medium. A source supplies instructions to be executed by a functional unit. A queue having a plurality of slots containing tags which are used for tagging instructions. A register file stores information required for the execution of each instruction at a location in the register file defined by the tag assigned to that instruction. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.
摘要翻译：一种标签监控系统，用于将标签分配给在有形计算机可读存储介质上的软件中实现的指令。源提供要由功能单元执行的指令。具有包含用于标记指令的标签的多个槽的队列。寄存器文件存储在由分配给该指令的标签定义的寄存器文件中的每个指令执行所需的信息。控制单元监视执行指令的完成，并且在执行指令完成后将标签推进队列。寄存器文件还包含多个读取地址使能端口和对应的读取输出端口。来自队列的每个时隙被耦合到对应的一个读取地址使能端口。因此，可以按照程序顺序从寄存器文件中读出每条指令的信息。

70. 发明授权

US06970995B2 System and method for register renaming 失效
标题翻译：用于注册重命名的系统和方法
公开(公告)号：US06970995B2
公开(公告)日：2005-11-29
申请号：US10222935
申请日：2002-08-19
申请人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
发明人： Trevor A. Deosaran , Sanjiv Garg , Kevin R. Iadonato
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.
摘要翻译：一种用于在具有用于存储要由处理器执行的指令组的可变提前指令窗口的处理器中执行寄存器重命名源寄存器的系统和方法，其中当位置变得可用时将新指令添加到可变提前指令窗口。标签被分配给变量提前指令窗口中的每个指令。离开窗口的每个指令的标签被分配给要添加到其中的下一个新指令。由处理器执行的指令的结果根据其相应的标签存储在临时缓冲器中，以避免输出和反依赖。因此，临时缓冲器允许处理器按顺序并行执行指令。仅对添加到变量提前指令窗口的每个新指令执行输入相关性的数据依赖性检查，并执行寄存器重命名以避免输入依赖关系。

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