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1. 发明授权

US5892963A System and method for assigning tags to instructions to control instruction execution 失效
标题翻译：将标签分配给用于控制指令执行的指令的系统和方法
公开(公告)号：US5892963A
公开(公告)日：1999-04-06
申请号：US799462
申请日：1997-02-13
申请人： Kevin Ray Iadonato , Trevor Anthony Deosaran , Sanjiv Garg
发明人： Kevin Ray Iadonato , Trevor Anthony Deosaran , Sanjiv Garg
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3857 , G06F9/3885
摘要： Tag monitoring system for assigning tags to instructions. A memory unit stores instructions to be executed by an execution unit. Before execution an instruction fetch unit decodes the instructions. A register file stores the decoded instructions. A queue having a plurality of slots containing tags which are used for tagging the decoded instructions. A control unit assigns the tags to decoded instructions, monitors the completion of executed instructions, and advances the tags in the queue upon completion of an executed instruction. The register stores a given decoded instruction at an address location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, a a decoded instruction is read out of a read output port enabled by the tag assigned to that decoded instruction in program order.
摘要翻译：标签监控系统，用于将标签分配给指令。存储单元存储由执行单元执行的指令。执行前，指令取出单元解码指令。寄存器文件存储解码的指令。具有包含用于标记解码指令的标签的多个时隙的队列。控制单元将标签分配给经解码的指令，监视执行指令的完成，并且在完成执行指令时将标签推进队列中。寄存器在由分配给该指令的标签定义的寄存器文件的地址位置处存储给定的解码指令。寄存器文件还包含多个读取地址使能端口和对应的读取输出端口。来自队列的每个时隙被耦合到对应的一个读取地址使能端口。因此，从由分配给该解码指令的标签启用的读取输出端口以编程顺序读出解码指令。

2. 发明授权

US07051187B2 Superscalar RISC instruction scheduling 失效
公开(公告)号：US07051187B2
公开(公告)日：2006-05-23
申请号：US10086197
申请日：2002-03-01
申请人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F9/38
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

3. 发明授权

US06289433B1 Superscalar RISC instruction scheduling 失效
标题翻译：超标量RISC指令调度
公开(公告)号：US06289433B1
公开(公告)日：2001-09-11
申请号：US09329354
申请日：1999-06-10
申请人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F1500
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependence check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependence check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括用于确定指令之间的数据依赖性的数据相关性检查电路。标签分配电路根据由数据相关性检查电路确定的数据相关性，生成更多标签之一以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

4. 发明授权

US07802074B2 Superscalar RISC instruction scheduling 失效
标题翻译：超标量RISC指令调度
公开(公告)号：US07802074B2
公开(公告)日：2010-09-21
申请号：US11730566
申请日：2007-04-02
申请人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F9/38
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括数据相关性检查电路，用于确定指令之间的数据依赖性。标签分配电路基于由数据相关性检查电路确定的数据依赖性，生成一个或多个标签以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

5. 发明授权

US5974526A Superscalar RISC instruction scheduling 失效
标题翻译：超标量RISC指令调度
公开(公告)号：US5974526A
公开(公告)日：1999-10-26
申请号：US990414
申请日：1997-12-15
申请人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括数据相关性检查电路以确定指令之间的数据依赖性。标签分配电路根据由数据依赖性检查电路确定的数据依赖性，生成更多标签之一以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

6. 发明授权

US5737624A Superscalar risc instruction scheduling 失效
标题翻译：超标量risc指令调度
公开(公告)号：US5737624A
公开(公告)日：1998-04-07
申请号：US594401
申请日：1996-01-31
申请人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependence check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependence check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括用于确定指令之间的数据依赖性的数据相关性检查电路。标签分配电路根据由数据相关性检查电路确定的数据相关性，生成更多标签之一以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

7. 发明授权

US07516305B2 System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor 失效
公开(公告)号：US07516305B2
公开(公告)日：2009-04-07
申请号：US11642625
申请日：2006-12-21
申请人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
发明人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.

8. 发明申请

US20090013155A1 System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor 失效
标题翻译：用于在超标量微处理器中同时退出一组指令的系统和方法
公开(公告)号：US20090013155A1
公开(公告)日：2009-01-08
申请号：US12212361
申请日：2008-09-17
申请人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
发明人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.
摘要翻译：一种用于在超标量微处理器中停止指令的系统和方法，该系统和方法执行包括具有预定程序顺序的一组指令的程序，所述退出系统用于同时停止由微处理器执行或不按顺序执行的指令组。退休系统包括：完成块，用于监视指令的状态以确定已经执行了哪个指令或指令组，用于确定每个执行的指令是否可取回的退出控制块;用于存储执行的指令结果的临时缓冲器程序顺序和用于存储可取样指令结果的寄存器阵列。此外，退休控制块还通过将其结果从临时缓冲器同时传送到寄存器阵列来进一步控制确定为可延展的一组指令的退役，并且通过将其结果直接存储在寄存器阵列中来依次执行的指令。该方法包括以下步骤：监视指令的状态以确定已经执行了哪组指令，确定每个被执行的指令是否可以被取消，将在程序顺序中执行的指令的结果存储在临时缓冲器中，存储可检索指令结果一个寄存器阵列，并通过将它们的结果从临时缓冲器同时传送到寄存器阵列，并且将其结果直接存储在寄存器阵列中，按顺序执行退出指令，并退出一组可重试指令。

9. 发明授权

US07430651B2 System and method for assigning tags to control instruction processing in a superscalar processor 失效
标题翻译：用于分配标签以控制超标量处理器中的指令处理的系统和方法
公开(公告)号：US07430651B2
公开(公告)日：2008-09-30
申请号：US11338817
申请日：2006-01-25
申请人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
发明人： Kevin R. Iadonato , Trevor A. Deosaran , Sanjiv Garg
IPC分类号： G09F15/00 , G09F9/30
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for tagging the instructions. The tags are arranged in the queue in an order specified by the program order of their corresponding instructions. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file stores an instruction's information at a location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.
摘要翻译：用于将标签分配给指令的标签监控系统。源提供要由功能单元执行的指令。寄存器文件存储执行每条指令所需的信息。具有包含用于标记指令的标签的多个槽的队列。标签按照其相应指令的程序顺序指定的顺序排列在队列中。控制单元监视执行指令的完成，并且在执行指令完成后将标签推进队列。寄存器文件将指令的信息存储在由分配给该指令的标签定义的寄存器文件中的位置处。寄存器文件还包含多个读取地址使能端口和对应的读取输出端口。来自队列的每个时隙被耦合到对应的一个读取地址使能端口。因此，可以按照程序顺序从寄存器文件中读出每条指令的信息。

10. 发明申请

US20080059770A1 Superscalar RISC instruction scheduling 失效
标题翻译：超标量RISC指令调度
公开(公告)号：US20080059770A1
公开(公告)日：2008-03-06
申请号：US11730566
申请日：2007-04-02
申请人： Sanjiv Garg , Kevin Iadonato , Le Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Iadonato , Le Nguyen , Johannes Wang
IPC分类号： G06F9/312
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括数据相关性检查电路，用于确定指令之间的数据依赖性。标签分配电路基于由数据相关性检查电路确定的数据依赖性，生成一个或多个标签以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

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