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61. 发明授权

US07522449B2 Phase change memory device and related programming method 有权
标题翻译：相变存储器件及相关编程方法
公开(公告)号：US07522449B2
公开(公告)日：2009-04-21
申请号：US11790011
申请日：2007-04-23
申请人： Yu-Hwan Ro , Kwang-Jin Lee , Sang-Beom Kang , Woo-Yeong Cho
发明人： Yu-Hwan Ro , Kwang-Jin Lee , Sang-Beom Kang , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C16/3486 , G11C2013/0076
摘要： In various methods of performing program operations in phase change memory devices, selected memory cells are repeatedly programmed to obtain resistance distributions having desired characteristics such as adequate sensing margins.
摘要翻译：在相变存储器件中执行程序操作的各种方法中，选择的存储器单元被重复编程以获得具有所需特性（例如足够的感测裕度）的电阻分布。

62. 发明申请

US20070236987A1 Phase change memory devices and systems, and related programming methods 有权
标题翻译：相变存储器件和系统以及相关编程方法
公开(公告)号：US20070236987A1
公开(公告)日：2007-10-11
申请号：US11727711
申请日：2007-03-28
申请人： Woo-Yeong Cho , Kwang-Jin Lee , Hye-Jin Kim
发明人： Woo-Yeong Cho , Kwang-Jin Lee , Hye-Jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/0078
摘要： A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.
摘要翻译：相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个存储单元与程序数据。

63. 发明授权

US08259511B2 Phase change memory device generating program current and method thereof 有权
标题翻译：相变存储器件产生程序电流及其方法
公开(公告)号：US08259511B2
公开(公告)日：2012-09-04
申请号：US13064672
申请日：2011-04-07
申请人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
发明人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.
摘要翻译：相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。存储单元阵列可以包括多个存储单元。写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

64. 发明授权

US08243542B2 Resistance variable memory devices and read methods thereof 有权
标题翻译：电阻变量存储器件及其读取方法
公开(公告)号：US08243542B2
公开(公告)日：2012-08-14
申请号：US12691769
申请日：2010-01-22
申请人： Junsoo Bae , Dueung Kim , Kwangjin Lee , Hyungrok Oh , Beakhyung Cho , Byunggil Choi , Woo-Yeong Cho , Yu-Hwan Ro
发明人： Junsoo Bae , Dueung Kim , Kwangjin Lee , Hyungrok Oh , Beakhyung Cho , Byunggil Choi , Woo-Yeong Cho , Yu-Hwan Ro
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C5/145 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0076 , G11C2013/0078 , G11C2213/72
摘要： A resistance-variable memory device includes memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell may, for example, include a resistance-variable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline using the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage.
摘要翻译：电阻可变存储器件包括存储单元，高压电路，预充电电路，偏置电路和读出放大器。每个存储单元可以例如包括电阻可变材料和连接到位线的二极管。高压电路从电源提供高电压。预充电电路将位线充电至电源电压后，将位线升高至高电压。偏置电路使用高电压向位线提供读取电流。读出放大器通过高电压将位线的电压与参考电压进行比较。

65. 发明授权

US07903448B2 Resistance random access memory having common source line 有权
标题翻译：具有共同源极线的电阻随机存取存储器
公开(公告)号：US07903448B2
公开(公告)日：2011-03-08
申请号：US11964142
申请日：2007-12-26
申请人： Hyung-Rok Oh , Sang-Beom Kang , Joon-Min Park , Woo-Yeong Cho
发明人： Hyung-Rok Oh , Sang-Beom Kang , Joon-Min Park , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.
摘要翻译：具有源线共享结构的电阻随机存取存储器（RRAM）和相关联的数据存取方法。其中通过具有相互相反方向的第一和第二写入路径来执行将第一状态和第二状态的数据写入所选存储单元的写入操作，包括字线，位线，存储单元阵列和多个源线。存储单元阵列包括多个存储单元，每个存储单元由耦合到电阻存储器件的存取晶体管构成。存储单元被布置成行和列的矩阵并且位于字线和位线的每个交叉点处。多个源极线中的每一个被设置在一对字线之间并且在与字线相同的方向上。在存储单元写入操作中，将正电压施加到源极线。通过源极线共享结构，占用的芯片面积减小，并且在写入操作模式中，可以在正电压电平范围内确定位线电位。

66. 发明申请

US20110042746A1 SINGLE TRANSISTOR MEMORY DEVICE HAVING SOURCE AND DRAIN INSULATING REGIONS AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：具有源极和漏极绝缘区域的单晶体管存储器件及其制造方法
公开(公告)号：US20110042746A1
公开(公告)日：2011-02-24
申请号：US12940304
申请日：2010-11-05
申请人： Nam-Kyun Tak , Ki-Whan Song , Chang-Woo Oh , Woo-Yeong Cho
发明人： Nam-Kyun Tak , Ki-Whan Song , Chang-Woo Oh , Woo-Yeong Cho
IPC分类号： H01L29/772
CPC分类号： H01L27/108 , H01L27/10802 , H01L29/0653 , H01L29/1045 , H01L29/7834 , H01L29/7841
摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.
摘要翻译：单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

67. 发明申请

US20070047295A1 Magnetic memory device and method of fabricating the same 失效
标题翻译：磁记忆装置及其制造方法
公开(公告)号：US20070047295A1
公开(公告)日：2007-03-01
申请号：US11480242
申请日：2006-06-30
申请人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： G11C11/00
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

68. 发明申请

US20050146929A1 Nonvolatile semiconductor memory device with scalable two transistor memory cells 有权
标题翻译：具有可伸缩双晶体管存储单元的非易失性半导体存储器件
公开(公告)号：US20050146929A1
公开(公告)日：2005-07-07
申请号：US10976626
申请日：2004-10-29
申请人： Woo-Yeong Cho , Byung-Gil Choi
发明人： Woo-Yeong Cho , Byung-Gil Choi
IPC分类号： G11C16/04 , G11C11/34 , G11C11/404 , G11C16/02 , H01L27/115
CPC分类号： G11C11/404
摘要： A nonvolatile memory device includes a bit line, a pair of data lines and a plurality of scalable two transistor memory (STTM) cells. The memory cells are arranged between a pair of datalines so as to share the bit line. The memory device further includes a data line selection circuit and a sense amplification circuit. The data line selection circuit selects one of a pair of data lines, and the sense amplification circuit senses and amplifies a voltage difference between the bit line and the selected data line. Operation speed is increased, while improving device cell array structure.
摘要翻译：非易失性存储器件包括位线，一对数据线和多个可伸缩双晶体管存储器（STTM）单元。存储单元布置在一对数据之间，以便共享位线。存储器件还包括数据线选择电路和读出放大电路。数据线选择电路选择一对数据线之一，并且感测放大电路感测并放大位线与所选数据线之间的电压差。操作速度提高，同时提高器件单元阵列结构。

69. 发明申请

US20110188303A1 Phase change memory device generating program current and mehtod thereof 有权
标题翻译：相变存储器件产生程序电流和电流
公开(公告)号：US20110188303A1
公开(公告)日：2011-08-04
申请号：US13064672
申请日：2011-04-07
申请人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
发明人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.
摘要翻译：相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。存储单元阵列可以包括多个存储单元。写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

70. 发明授权

US07936612B2 Phase change memory device generating program current and method thereof 有权
标题翻译：相变存储器件产生程序电流及其方法
公开(公告)号：US07936612B2
公开(公告)日：2011-05-03
申请号：US12654338
申请日：2009-12-17
申请人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
发明人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.
摘要翻译：相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。存储单元阵列可以包括多个存储单元。写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

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