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61. 发明申请

US20080246161A1 Damascene conductive line for contacting an underlying memory element 有权
公开(公告)号：US20080246161A1
公开(公告)日：2008-10-09
申请号：US12157086
申请日：2008-06-06
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L23/535
CPC分类号： H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element.

62. 发明授权

US07323707B2 Initializing phase change memories 有权
公开(公告)号：US07323707B2
公开(公告)日：2008-01-29
申请号：US10881664
申请日：2004-06-30
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L29/02
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the set or low resistance state, into the reset or high resistance state. In one advantageous embodiment, after such initialization and programming, the threshold voltage increase is eliminated so that the cells operate thereafter without the added threshold voltage.

63. 发明授权

US06990017B1 Accessing phase change memories 有权
标题翻译：访问相变存储器
公开(公告)号：US06990017B1
公开(公告)日：2006-01-24
申请号：US10882860
申请日：2004-06-30
申请人： Ward D. Parkinson , Charles H. Dennison , Stephen Hudgens
发明人： Ward D. Parkinson , Charles H. Dennison , Stephen Hudgens
IPC分类号： H01L21/336
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/74 , G11C2213/76
摘要： A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.
摘要翻译：存储器可以包括相变存储器元件和串联连接的第一和第二选择器件。第二选择装置可以具有比第一选择装置更高的电阻和更大的阈值电压。在一个实施例中，第一选择装置可以具有基本上等于其保持电压的阈值电压。在一些实施例中，选择装置和存储元件可以由硫族化物制成。在一些实施例中，选择装置可以由不可编程的硫族化物制成。具有较高阈值电压的选择装置可能会对组合造成较低的泄漏，但也可能表现出增加的快速恢复。这种增加的快速恢复可以被具有较低阈值电压的选择装置抵消，导致在一些实施例中与低泄漏和高性能的组合。

64. 发明授权

US06924190B2 Use of gate electrode workfunction to improve DRAM refresh 失效
公开(公告)号：US06924190B2
公开(公告)日：2005-08-02
申请号：US10279094
申请日：2002-10-24
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： G11C11/406 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10873 , G11C11/406 , H01L27/10811
摘要： This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.

65. 发明授权

US06897542B2 Semiconductor assemblies 失效
公开(公告)号：US06897542B2
公开(公告)日：2005-05-24
申请号：US10630114
申请日：2003-07-29
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L21/763 , H01L21/768 , H01L23/31 , H01L23/485 , H01L23/525 , H01L29/00
CPC分类号： H01L21/76831 , H01L21/763 , H01L21/76802 , H01L23/3171 , H01L23/485 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material. The invention also includes a semiconductor assembly comprising an anti-fuse construction and an electrically conductive interconnect construction.

66. 发明授权

US06778453B2 METHOD OF STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD OF MODIFYING OPERATION OF DYNAMIC RANDOM ACCESS MEMORY IN RESPONSE TO TEMPERATURE, PROGRAMMABLE TEMPERATURE SENSING CIRCUIT AND MEMORY INTEGRATED CIRCUIT 失效
标题翻译：在集成电路中存储温度阈值的方法，对温度，可编程温度感测电路和存储器集成电路进行动态随机存取存储器操作的修改方法
公开(公告)号：US06778453B2
公开(公告)日：2004-08-17
申请号：US10373498
申请日：2003-02-24
申请人： Christopher B. Cooper , Ming-Bo Liu , Chris G. Martin , Troy A. Manning , Stephen L. Casper , Charles H. Dennison , Brian M. Shirley , Brian L. Brown , Shubneesh Batra
发明人： Christopher B. Cooper , Ming-Bo Liu , Chris G. Martin , Troy A. Manning , Stephen L. Casper , Charles H. Dennison , Brian M. Shirley , Brian L. Brown , Shubneesh Batra
IPC分类号： G11C704
CPC分类号： G11C7/04 , G11C7/1045 , G11C7/20 , G11C11/4072 , G11C11/4078
摘要： A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses.
摘要翻译：一种用于在集成电路中存储温度阈值的方法包括：测量集成电路的相对于温度的操作参数，计算集成电路性能超过预定规格的最大温度，并将集成电路性能中最高温度的参数存储在集成电路中的比较电路中通过在比较电路中选择性地吹入可熔设备。可熔断器件可以是反熔丝。

67. 发明授权

US06753241B2 Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry 失效
标题翻译：形成接触开口的半导体加工方法，形成电连接和互连的方法以及集成电路
公开(公告)号：US06753241B2
公开(公告)日：2004-06-22
申请号：US09956274
申请日：2001-09-18
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L213205
CPC分类号： H01L23/485 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.
摘要翻译：描述形成接触开口，制造电互连和相关集成电路的方法。还描述了通过一个或多个本发明方法形成的集成电路。在一个实施方式中，在衬底外表面上形成具有需要电连通的接触焊盘的导电浇道或管线。导电插塞横向靠近接触垫形成，并与之一起形成有效加宽的接触垫。导电材料形成在接触开口内，接触开口被接纳在有效加宽的接触垫上的绝缘材料内。在优选的实施方式中，一对导电插塞形成在接触垫的两侧在其附近。导电插塞可以远离衬底外表面延伸一个或多或小于形成插头的导线的导线高度的距离。在前一种情况下，并且根据一个方面，这种插头可以包括与相关导电线的接触垫重叠的部分。

68. 发明授权

US06673700B2 Reduced area intersection between electrode and programming element 有权
标题翻译：电极与编程元件之间的减少交点
公开(公告)号：US06673700B2
公开(公告)日：2004-01-06
申请号：US09895020
申请日：2001-06-30
申请人： Charles H. Dennison , Guy C. Wicker , Tyler A. Lowrey , Stephen J. Hudgens , Chien Chiang , Daniel Xu
发明人： Charles H. Dennison , Guy C. Wicker , Tyler A. Lowrey , Stephen J. Hudgens , Chien Chiang , Daniel Xu
IPC分类号： H01L21326
CPC分类号： H01L27/2463 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method comprising forming a sacrificial layer over less than the entire portion of a contact area on a substrate, the sacrificial layer having a thickness defining an edge over the contact area, forming a spacer layer over the spacer, the spacer layer conforming to the shape of the first sacrificial layer such that the spacer layer comprises an edge portion over the contact area adjacent the first sacrificial layer edge, removing the sacrificial layer, while retaining the edge portion of the spacer layer over the contact area, forming a dielectric layer over the contact area, removing the edge portion, and forming a programmable material to the contact area formerly occupied by the edge portion. An apparatus comprising a volume of programmable material, a conductor, and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area at one end coupled to the volume of programmable material, wherein the contact area is less than the surface area at the one end.
摘要翻译：一种方法，包括在小于衬底上的接触区域的整个部分上形成牺牲层，所述牺牲层具有限定在所述接触区域上的边缘的厚度，在所述间隔物上形成间隔层，所述隔离层符合形状的第一牺牲层，使得间隔层包括邻近第一牺牲层边缘的接触区域上的边缘部分，去除牺牲层，同时将间隔物层的边缘部分保持在接触区域上方，形成介于第接触区域，去除边缘部分，并且将可编程材料形成到以前由边缘部分占据的接触区域。一种包括可编程材料体积，导体和设置在所述可编程材料体积与所述导体之间的电极的装置，所述电极在一端与所述可编程材料的体积相连接的接触区域，其中所述接触面积小于一端的表面积。

69. 发明授权

US06620672B1 SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation 失效
标题翻译： SOI DRAM具有采用自对准穿透存储节点接触形成的数字线下的埋入式电容器
公开(公告)号：US06620672B1
公开(公告)日：2003-09-16
申请号：US10140328
申请日：2002-05-08
申请人： Charles H. Dennison , John K. Zahurak
发明人： Charles H. Dennison , John K. Zahurak
IPC分类号： H01L218242
CPC分类号： H01L27/10858 , H01L21/84 , H01L27/10888 , H01L27/10894 , H01L27/1203
摘要： A method of fabricating a memory cell is described in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack which includes a gate region electrically connected with a word line. At least one capacitor is formed con a first side of the substrate and is electrically connected to one of the source and drain regions. At least one bit line conductor is formed on the reverse or flip side of the substrate, wherein the bit line conductor is electrically connected to the other of the source and drain regions. Self-aligned contact openings are formed through insulative material over the substrate to provide vias for the electrical connections for each of the capacitor and bit line conductor. These contact openings and the deposited contact material are substantially preserved throughout the entire fabrication process.
摘要翻译：描述了一种制造存储单元的方法，其中首先在SOI衬底上形成存取晶体管。存取晶体管包含在衬底的半导体材料层中的源极和漏极区域，以及至少一个栅极叠层，其包括与字线电连接的栅极区域。在衬底的第一侧上形成至少一个电容器，并且电连接到源区和漏区之一。至少一个位线导体形成在衬底的反面或反面上，其中位线导体电连接到源极和漏极区域中的另一个。自对准接触开口通过衬底上的绝缘材料形成，以为电容器和位线导体中的每一个提供用于电连接的通路。这些接触开口和沉积的接触材料在整个制造过程中基本保持不变。

70. 发明授权

US06605527B2 Reduced area intersection between electrode and programming element 有权
公开(公告)号：US06605527B2
公开(公告)日：2003-08-12
申请号：US09896531
申请日：2001-06-30
申请人： Charles H. Dennison , Alice T. Wang , Patel Kanaiyalal Chaturbhai , Jenn C. Chow
发明人： Charles H. Dennison , Alice T. Wang , Patel Kanaiyalal Chaturbhai , Jenn C. Chow
IPC分类号： H01L214763
CPC分类号： H01L27/1021 , H01L21/761 , H01L27/24
摘要： A method comprising forming a first dielectric layer over an electrode formed to a first contact point on a substrate, the electrode having a contact area; patterning the first dielectric layer into a body, a thickness of the first dielectric layer defining a side wall; forming at least one spacer along the side wall of the first dielectric body, the at least one spacer overlying a portion of the contact area; forming a second dielectric layer on the contact area; removing the at least one spacer; and forming a material comprising a second contact point to the contact area. An apparatus comprising a volume of programmable material; a conductor; and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area coupled to the volume of programmable material.

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