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61. 发明授权

US06265256B1 MOS transistor with minimal overlap between gate and source/drain extensions 有权
标题翻译： MOS晶体管在栅极和源极/漏极延伸之间具有最小的重叠
公开(公告)号：US06265256B1
公开(公告)日：2001-07-24
申请号：US09156238
申请日：1998-09-17
申请人： Judy Xilin An , Bin Yu , Yowjuang W. Liu
发明人： Judy Xilin An , Bin Yu , Yowjuang W. Liu
IPC分类号： H01L218238
CPC分类号： H01L29/66545 , H01L21/28123 , H01L21/823468 , H01L29/6659
摘要： A method for making a ULSI MOSFET includes establishing a gate void in a field oxide layer above a silicon substrate, after source and drain regions with associated source and drain extensions have been established in the substrate. A gate electrode is deposited in the void and gate spacers are likewise deposited in the void on the sides of the gate electrode, such that the gate electrode is spaced from the walls of the void. The spacers, not the gate electrode, are located above the source/drain extensions, such that fringe coupling between the gate electrode and the source and drain extensions is suppressed.
摘要翻译：制造ULSI MOSFET的方法包括：在衬底中建立具有相关源极和漏极延伸部分的源极和漏极区域之后，在硅衬底上的场氧化物层中建立栅极空隙。栅电极沉积在空隙中，并且栅极间隔物同样沉积在栅电极的侧面上的空隙中，使得栅电极与空隙的壁间隔开。间隔件而不是栅电极位于源极/漏极延伸部上方，从而抑制栅极电极和源极和漏极延伸部之间的边缘耦合。

62. 发明授权

US06225161B1 Fully recessed semiconductor method for low power applications with single wrap around buried drain region 有权
标题翻译：用于低功率应用的全凹陷式半导体方法，其中单个环绕埋漏区
公开(公告)号：US06225161B1
公开(公告)日：2001-05-01
申请号：US09470568
申请日：1999-12-22
申请人： Yowjuang W. Liu , Donald L. Wollesen
发明人： Yowjuang W. Liu , Donald L. Wollesen
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L29/42336 , H01L29/7883 , Y10S257/905
摘要： A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate. In one embodiment of the present invention the buried drain region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a drain junction disposed along portions of the sidewall and bottom of the trench, and the buried source region has a lower boundary which is approximately less than the depth of the trench. In another embodiment of the present invention the buried source region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a source junction disposed along portions of the sidewall and bottom of the trench, and the buried drain region has a lower boundary which is approximately less than the depth of the trench. In one embodiment of the present invention, sidewall dopings are formed in the substrate to shield the trenched control gate from the buried source and buried drain regions.
摘要翻译：用于低功率应用的完全凹陷的器件结构和方法包括沟槽浮动栅极，沟槽控制栅极和围绕埋漏区的单个环绕。沟槽浮置栅极和沟槽控制栅极形成在蚀刻到半导体衬底中的阱结区域中的单个沟槽中，以提供基本平坦的形貌。完全凹陷结构还包括掩埋源区和埋入漏极区，每个掩埋漏极区形成在由沟槽横向隔开的阱结区域中。掩埋源极区域和掩埋漏极区域的上边界与沟槽浮动栅极的顶表面的深度大致相同。在本发明的一个实施例中，埋漏区具有下部边界，其部分地在沟槽底表面下方延伸，以形成沿着沟槽的侧壁和底部的一部分设置的漏极结，并且埋入源区具有下边界大约小于沟槽的深度。在本发明的另一个实施例中，掩埋源区具有下部边界，其部分地在沟槽的底表面下方延伸地形成沿着沟槽的侧壁和底部的部分设置的源极结，而漏极区域具有下边界大约小于沟槽的深度。在本发明的一个实施例中，在衬底中形成侧壁掺杂，以将沟槽的控制栅极与掩埋源和埋漏区区隔开。

63. 发明授权

US06180441B2 Bar field effect transistor 有权
标题翻译：棒场效应晶体管
公开(公告)号：US06180441B2
公开(公告)日：2001-01-30
申请号：US09307698
申请日：1999-05-10
申请人： John T. Yue , Matthew S. Buynoski , Yowjuang W. Liu , Peng Fang
发明人： John T. Yue , Matthew S. Buynoski , Yowjuang W. Liu , Peng Fang
IPC分类号： H01L21336
CPC分类号： H01L29/66636 , B82Y10/00 , H01L21/26586 , H01L29/41766 , H01L29/66439 , H01L29/66575 , H01L29/66621 , H01L29/66795 , H01L29/785 , H01L29/7853 , H01L29/7854
摘要： A field effect transistor is formed across a one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.
摘要翻译：在一个或多个沟槽（26）或条（120）上形成场效应晶体管，从而增加了沟道区的有效宽度和器件的载流能力。

64. 发明授权

US06169302A Determination of parasitic capacitance between the gate and drain/source local interconnect of a field effect transistor 失效
标题翻译：确定场效应晶体管的栅极和漏极/源局部互连之间的寄生电容
公开(公告)号：US06169302A
公开(公告)日：2001-01-02
申请号：US09361698
申请日：1999-07-27
申请人： Wei Long , Qi Xiang , Yowjuang W. Liu
发明人： Wei Long , Qi Xiang , Yowjuang W. Liu
IPC分类号： H01L2358
CPC分类号： H01L22/34 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： The present invention accurately determines a first parasitic capacitance component between a conductive gate region to a drain local interconnect of a real field effect transistor, and determines a second parasitic capacitance component between the conductive gate region to a source local interconnect of the real field effect transistor. A virtual field effect transistor is fabricated on a dielectric in order to determine the parasitic capacitance component between just the gate and the drain or source local interconnect of the real field effect transistor. The virtual field effect transistor includes a virtual drain local interconnect, a virtual source local interconnect, and a virtual conductive gate region fabricated on the dielectric with a respective size and positions relative to each other that are substantially the same as that of the drain and source local interconnects and the gate, respectively, of the real field effect transistor. In this manner, the first parasitic capacitance component between the conductive gate region of the real field effect transistor to the drain local interconnect of the real field effect transistor is a first capacitance measured between the virtual conductive gate region and the virtual drain local interconnect of the virtual field effect transistor of the present invention. Similarly, the second parasitic capacitance component between the conductive gate region of the real field effect transistor to the source local interconnect of the real field effect transistor is a second capacitance measured between the virtual conductive gate region and the virtual source local interconnect of the virtual field effect transistor of the present invention.
摘要翻译：本发明精确地确定实际场效应晶体管的导电栅极与漏极局部互连之间的第一寄生电容分量，并且确定导电栅区与实场效应晶体管的源局部互连之间的第二寄生电容分量。在电介质上制造虚拟场效应晶体管，以便确定真实场效应晶体管的栅极和漏极或源局部互连之间的寄生电容分量。虚拟场效应晶体管包括虚拟漏极局部互连，虚拟源局部互连和在电介质上制造的虚拟导电栅极区域，该虚拟导电栅极区域具有与漏极和源极基本上相同的尺寸和位置分别是实际场效应晶体管的局部互连和栅极。以这种方式，实际场效应晶体管的导电栅极区域与实场效应晶体管的漏极局部互连之间的第一寄生电容分量是在虚拟导电栅极区域和虚拟漏极局部互连之间测量的第一电容虚拟场效应晶体管。类似地，实场效应晶体管的导电栅极区域与实场效应晶体管的源局部互连之间的第二寄生电容分量是在虚拟导电栅极区域和虚拟场虚拟源局部互连之间测量的第二电容效应晶体管。

65. 发明授权

US6118147A Double density non-volatile memory cells 失效
标题翻译：双密度非易失性存储单元
公开(公告)号：US6118147A
公开(公告)日：2000-09-12
申请号：US110446
申请日：1998-07-07
申请人： Yowjuang W. Liu
发明人： Yowjuang W. Liu
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/76 , H01L29/88
CPC分类号： H01L27/11553 , H01L27/115
摘要： Double density non-volatile memory cells having a trench structure are formed in a substrate, thereby facilitating miniaturization, improved planarization and low power programming and erasing. Each double density cell comprises two floating gates and a common control gate. Each pair of double density cells shares a common source region. Embodiments include forming first and second trenches in a substrate and depositing a tunnel dielectric layer in each trench. Polycrystalline silicon is then deposited filling each trench and a hole is etched forming two floating gate electrodes in each trench. An interpoly dielectric layer is then formed and a substantially T-shaped control gate electrode is deposited filling the hole between the floating gates and extending on the substrate.
摘要翻译：在衬底中形成具有沟槽结构的双重密度非易失性存储单元，从而便于小型化，改进的平面化和低功率编程和擦除。每个双密度单元包括两个浮动栅极和公共控制栅极。每对双密度细胞共享一个共同的源区。实施例包括在衬底中形成第一和第二沟槽，并在每个沟槽中沉积隧道介电层。然后沉积多晶硅填充每个沟槽，并且蚀刻孔，在每个沟槽中形成两个浮置栅电极。然后形成间隔电介质层，并且沉积基本上T形的控制栅极，填充浮置栅极之间的孔并在衬底上延伸。

66. 发明授权

US6097061A Trenched gate metal oxide semiconductor device and method 失效
标题翻译：沟槽式金属氧化物半导体器件及方法
公开(公告)号：US6097061A
公开(公告)日：2000-08-01
申请号：US52051
申请日：1998-03-30
申请人： Yowjuang W. Liu , Donald L. Wollesen
发明人： Yowjuang W. Liu , Donald L. Wollesen
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49 , H01L29/76 , H01L27/108 , H01L29/94
CPC分类号： H01L29/78 , H01L29/66621 , H01L29/4933
摘要： A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region, a drain region, and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment, the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment, the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.
摘要翻译：金属氧化物半导体（MOS）晶体管和用于改进器件缩放的方法包括形成在半导体衬底内蚀刻的沟槽内的沟槽多晶硅栅极，还包括源极区，漏极区和沟道区。源极和漏极区域被形成沟槽的多晶硅栅极的沟槽横向分开，并且部分地在沟槽的底表面下方延伸。沟槽区域形成在沟槽底面下方的硅衬底中。在一个实施例中，沟槽多晶硅栅极的顶表面基本上平行于衬底表面。在另一个实施例中，沟槽多晶硅栅极的顶表面和一部分设置在衬底表面上方。

67. 发明授权

US5990515A Trenched gate non-volatile semiconductor device and method with corner doping and sidewall doping 失效
标题翻译：倾斜门非易失性半导体器件和方法与角掺杂和侧壁掺杂
公开(公告)号：US5990515A
公开(公告)日：1999-11-23
申请号：US52062
申请日：1998-03-30
申请人： Yowjuang W. Liu , Donald L. Wollesen
发明人： Yowjuang W. Liu , Donald L. Wollesen
IPC分类号： H01L21/336 , H01L29/423 , H01L29/72
CPC分类号： H01L29/66825 , H01L29/42336
摘要： A non-volatile semiconductor cell structure and method comprises a trenched floating gate, a sidewall doping and a corner doping and further includes a sidewall doped region, a corner doped region, a channel region, and an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate. In a preferred embodiment, the trenched floating gate has a top surface which is substantially planar with a top surface of the semiconductor substrate. The control gate and the inter-gate dielectric are formed on the top surface of the trenched floating gate. The sidewall doped region and the corner doped region are laterally separated by the trench in which the trenched floating gate is formed. The sidewall doped region has a depth which is greater than the depth of the trench, and the corner doped region has a depth which is less than the depth of the trench. The sidewall doping is a diffusion region formed in the sidewall doped region of the semiconductor substrate and is immediately contiguous to a vertical sidewall of the trench and immediately contiguous to the substrate surface. The corner doping is a diffusion region formed in the corner doped region of the semiconductor substrate and is immediately contiguous the upper vertical sidewall of the trench which is opposite the vertical sidewall along which the sidewall doping is formed and is immediately contiguous the substrate surface.
摘要翻译：非挥发性半导体单元结构和方法包括沟槽浮置栅极，侧壁掺杂和角掺杂，并且还包括侧壁掺杂区域，角掺杂区域，沟道区域和栅极间介电层，以及控制门。沟槽浮栅形成在蚀刻到半导体衬底中的沟槽中。在优选实施例中，沟槽浮动栅极具有与半导体衬底的顶表面基本平坦的顶表面。控制栅极和栅极间电介质形成在沟槽浮动栅极的顶表面上。侧壁掺杂区域和拐角掺杂区域被形成有沟槽浮动栅极的沟槽横向分开。所述侧壁掺杂区域的深度大于所述沟槽的深度，并且所述拐角掺杂区域的深度小于所述沟槽的深度。侧壁掺杂是形成在半导体衬底的侧壁掺杂区域中的扩散区域，并且紧邻于沟槽的垂直侧壁并且紧邻衬底表面。角掺杂是形成在半导体衬底的角掺杂区域中的扩散区域，并且立即与沟槽的上垂直侧壁邻接，该垂直侧壁与形成侧壁掺杂的垂直侧壁相对，并且立即与衬底表面相邻。

68. 发明授权

US5955767A Semiconductor device with self-aligned insulator 失效
标题翻译：具有自对准绝缘体的半导体器件
公开(公告)号：US5955767A
公开(公告)日：1999-09-21
申请号：US907452
申请日：1997-08-08
申请人： Yowjuang W. Liu , Feng Qian , Tze-Kwai Kelvin Lai
发明人： Yowjuang W. Liu , Feng Qian , Tze-Kwai Kelvin Lai
IPC分类号： H01L21/762 , H01L21/8238 , H01L27/092 , H01L29/76 , H01L27/01
CPC分类号： H01L27/0922 , H01L21/76264 , H01L21/823878 , H01L27/0921 , H01L21/76267 , H01L21/76281
摘要： A semiconductor device having the advantages of an SOI structure without the attendant disadvantages is obtained by implanting oxygen ions using the gate electrode as a mask, and heating to form thin, self-aligned buried oxide regions extending from a field oxide region under source/drain regions self-aligned with the side surfaces of the gate electrode. In other embodiments, the thin buried oxide layer extends from a point in close proximity to the field oxide region and/or partially under the gate electrode.
摘要翻译：具有SOI结构的优点的半导体器件没有伴随的缺点是通过使用栅电极作为掩模注入氧离子，并且加热以形成从源极/漏极的场氧化物区域延伸的薄的自对准掩埋氧化物区域区域与栅电极的侧表面自对准。在其他实施例中，薄的掩埋氧化物层从靠近场氧化物区域的点和/或部分地在栅电极下方延伸。

69. 发明授权

US5777370A Trench isolation of field effect transistors 失效
标题翻译：沟道隔离场效应晶体管
公开(公告)号：US5777370A
公开(公告)日：1998-07-07
申请号：US662217
申请日：1996-06-12
申请人： Farrokh Kia Omid-Zohoor , Andre Stolmeijer , Yowjuang W. Liu , Craig Steven Sander
发明人： Farrokh Kia Omid-Zohoor , Andre Stolmeijer , Yowjuang W. Liu , Craig Steven Sander
IPC分类号： H01L21/762 , H01L29/76 , H01L29/94
CPC分类号： H01L21/76237
摘要： A method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics by junction leakage, breakdown or shorting when a metal silicide is used in the source/drain regions. A silicon wafer, is formed with a gate electrode material on a gate insulating layer before forming the trenches for isolation. Now, with an etch protective layer on the gate electrode, trenches are etched and filled with an insulating material in the gate electrode material, the gate insulating layer and the silicon wafer to isolate the active regions. After the gate electrode material is etched to define the gate electrodes, the tops of gate electrodes are in essentially the same plane as the tops of the trenches. Preferably in the fabrication process, sidewalls are formed on the walls of the trenches and the gate electrodes. This elevated trench structure prevents parasitic edge transistors and eliminates any possibly of junction leakage or shorting.
摘要翻译：一种制造具有沟槽而没有寄生边缘晶体管的集成电路的方法，用于在FET /漏极区域中使用金属硅化物时，将FET晶体管彼此隔离，而不会使FET工作特性受到结漏，击穿或短路的影响。在形成用于隔离的沟槽之前，在栅极绝缘层上形成具有栅电极材料的硅晶片。现在，在栅电极上具有蚀刻保护层，在栅电极材料，栅极绝缘层和硅晶片中蚀刻并填充绝缘材料的沟槽以隔离有源区。在栅电极材料被蚀刻以限定栅电极之后，栅电极的顶部与沟槽的顶部基本上在相同的平面中。优选地，在制造工艺中，在沟槽和栅电极的壁上形成侧壁。这种升高的沟槽结构防止寄生边缘晶体管，并消除任何可能的结漏电或短路。

70. 发明授权

US5672524A Three-dimensional complementary field effect transistor process 失效
标题翻译：三维互补场效应晶体管工艺
公开(公告)号：US5672524A
公开(公告)日：1997-09-30
申请号：US509911
申请日：1995-08-01
申请人： Yowjuang W. Liu , Yu Sun
发明人： Yowjuang W. Liu , Yu Sun
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7834 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/4238 , Y10S148/05
摘要： A field effect transistor has a short gate and is fabricated by: doping the bottom surface of a depression to form a relatively lightly doped region in the bottom of the depression; forming the gate of the field effect transistor on the sidewall of the depression such that the gate is insulated from the sidewall by a thin insulating layer; and implanting dopants to form the drain region and the source region of the transistor using the gate to mask a part of the relatively lightly doped region. The part of the relatively lightly doped region which is masked by the gate during implanting of the source and drain regions constitutes a lightly doped drain region of the transistor. The drain of the transistor is formed into the bottom of the depression. The length of the gate is primarily determined by the depth and/or profile of the sidewall. The source-to-drain on-resistance of the transistor is low because the transistor does not have a lightly doped source region. The transistor has high quality gate oxide because the sidewall of the depression upon which the gate oxide is grown is substantially free of ion impact damage.
摘要翻译：场效应晶体管具有短栅极，并且通过以下方式制造：掺杂凹陷的底表面以在凹陷的底部形成相对轻掺杂的区域; 在凹陷的侧壁上形成场效应晶体管的栅极，使得栅极通过薄绝缘层与侧壁绝缘; 以及使用所述栅极注入掺杂剂以形成所述晶体管的漏极区域和源极区域以掩蔽所述相对轻掺杂区域的一部分。在注入源极和漏极区域期间被栅极掩蔽的相对轻掺杂区域的部分构成晶体管的轻掺杂漏极区。晶体管的漏极形成凹陷的底部。栅极的长度主要由侧壁的深度和/或轮廓确定。晶体管的源极到漏极导通电阻很低，因为晶体管不具有轻掺杂的源极区域。晶体管具有高质量的栅极氧化物，因为其上生长栅极氧化物的凹陷的侧壁基本上没有离子冲击损伤。

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