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61. 发明授权

US06864520B2 Germanium field effect transistor and method of fabricating the same 有权
标题翻译：锗场效应晶体管及其制造方法
公开(公告)号：US06864520B2
公开(公告)日：2005-03-08
申请号：US10116568
申请日：2002-04-04
申请人： Massimo V. Fischetti , Steven E. Laux , Paul M. Solomon , Hon-Sum Philip Wong
发明人： Massimo V. Fischetti , Steven E. Laux , Paul M. Solomon , Hon-Sum Philip Wong
IPC分类号： H01L27/08 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/10 , H01L29/423 , H01L29/786 , H01L27/148
CPC分类号： H01L29/7853 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1037 , H01L29/42384 , H01L29/78618 , H01L29/78684
摘要： A method (and structure) for an electronic chip having at least one layer of material for which a carrier mobility of a first carrier type is higher in a first crystal surface than in a second crystal surface and for which a carrier mobility of a second carrier type is higher in the second crystal surface than the first crystal surface includes a first device having at least one component fabricated on the first crystal surface of the material, wherein an activity of the component of the first device involves primarily the first carrier type, and a second device having at least one component fabricated on the second crystal surface of the material, wherein an activity of the component of the second device involves primarily the second carrier type.
摘要翻译：一种用于电子芯片的方法（和结构），其具有至少一层材料，第一载体类型的载流子迁移率在第一晶体表面中高于第二晶体表面，并且第二载体的载流子迁移率类型在第二晶体表面比第一晶体表面高，包括具有在材料的第一晶体表面上制造的至少一个部件的第一器件，其中第一器件的元件的活性主要包括第一载流子类型，以及具有在所述材料的第二晶体表面上制造的至少一个部件的第二装置，其中所述第二装置的部件的活动主要涉及所述第二载体型。

62. 发明授权

US06803266B2 Process for passivating the semiconductor-dielectric interface of a MOS device and MOS device formed thereby 失效
标题翻译：钝化MOS器件的半导体介质接口和由此形成的MOS器件的工艺
公开(公告)号：US06803266B2
公开(公告)日：2004-10-12
申请号：US10249184
申请日：2003-03-20
申请人： Paul M. Solomon , Douglas A. Buchanan , Eduard A. Cartier , Kathryn W. Guarini , Fenton R. McFeely , Huiling Shang , John J. Yourkas
发明人： Paul M. Solomon , Douglas A. Buchanan , Eduard A. Cartier , Kathryn W. Guarini , Fenton R. McFeely , Huiling Shang , John J. Yourkas
IPC分类号： H01L21336
CPC分类号： H01L29/517 , H01L21/263 , H01L21/28079 , H01L29/495 , Y10S438/91
摘要： A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface. Three general approaches are encompassed: forming an aluminum-tungsten electrode stack in the presence of hydrogen so as to store atomic hydrogen between the tungsten and aluminum layers, followed by an anneal to cause the atomic hydrogen to diffuse through the tungsten layer and into the interface; subjecting a tungsten electrode to hydrogen plasma, during which atomic hydrogen diffuses through the electrode and into the semiconductor-dielectric interface; and implanting atomic hydrogen into tungsten electrode, followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.
摘要翻译：一种用于钝化MOS结构的半导体 - 电介质界面以将界面态密度降低到非常低的水平的方法。具体的示例是具有钨电极的MOSFET，其过去已经阻止下面的半导体 - 电介质界面的钝化达到足以将界面态密度降低到小于5×10 10 / cm 2 -eV的程度。虽然基本上不透分子氢，但是显示出薄钨层可以透过原子氢，使原子氢能够通过钨电极扩散到下面的半导体 - 电介质界面。包括三种一般方法：在氢的存在下形成铝 - 钨电极堆叠，以便在钨和铝层之间存储原子氢，随后进行退火，使原子氢扩散通过钨层并进入界面 ; 使钨电极经受氢等离子体，其中原子氢通过电极扩散并进入半导体 - 电介质界面; 并将原子氢注入钨电极中，随后进行退火，使原子氢扩散通过电极并进入半导体 - 电介质界面。

63. 发明授权

US06797604B2 Method for manufacturing device substrate with metal back-gate and structure formed thereby 有权
标题翻译：制造具有金属背栅的器件衬底和由此形成的结构的方法
公开(公告)号：US06797604B2
公开(公告)日：2004-09-28
申请号：US09817120
申请日：2001-03-27
申请人： Kevin K. Chan , Lijuan Huang , Fenton R. McFeely , Paul M. Solomon , Hon-Sum Philip Wong
发明人： Kevin K. Chan , Lijuan Huang , Fenton R. McFeely , Paul M. Solomon , Hon-Sum Philip Wong
IPC分类号： H01L214763
CPC分类号： H01L29/66772 , H01L21/76251 , H01L29/78648
摘要： A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.
摘要翻译：形成半导体器件的方法（和结果）包括在衬底和金属背栅上形成金属反向栅极，在金属背栅上形成钝化层，以防止金属背栅极反应具有自由基物质，并且在基材和金属背栅之间提供中间胶合层以增强粘合性。

64. 发明授权

US06762101B2 Damascene double-gate FET 有权
标题翻译：大马士革双栅FET
公开(公告)号：US06762101B2
公开(公告)日：2004-07-13
申请号：US10411727
申请日：2003-04-11
申请人： Kevin K. Chan , Erin C. Jones , Paul M. Solomon , Hon-Sum Phillip Wong
发明人： Kevin K. Chan , Erin C. Jones , Paul M. Solomon , Hon-Sum Phillip Wong
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/4908 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.
摘要翻译：使用大马士革式替代栅极处理步骤提供双栅极场效应晶体管（DGFET），以在先前形成的沟槽内部产生侧壁源极/漏极区域，氧化物间隔物和栅极结构。大马士革式的替代栅极处理步骤允许制造在触点下方具有较厚主体的锥形晶体管主体区域，从而降低访问阻力。

65. 发明授权

US06333247B1 Two-step MOSFET gate formation for high-density devices 失效
标题翻译：用于高密度器件的两级MOSFET栅极形成
公开(公告)号：US06333247B1
公开(公告)日：2001-12-25
申请号：US09501225
申请日：2000-02-10
申请人： Kevin K. Chan , Erin C. Jones , Paul M. Solomon
发明人： Kevin K. Chan , Erin C. Jones , Paul M. Solomon
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/76838 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66772 , H01L29/78648
摘要： A method of manufacturing a metal-oxide-semiconductor field effect transistor MOSFET device gate includes patterning and etching the mesa of a gate material. A dielectric layer is formed on the mesa and is planarized using chemical mechanical polishing (CMP). The active gate dimension is patterned and etched to form source and drain wells that extend down to an active area on either side of the MOSFET gate. In one further embodiment, the wells are filled with metal and the metal is planarized. The MOSFET device, in one embodiment, includes source and drain wells equally spaced from the active gate.
摘要翻译：制造金属氧化物半导体场效应晶体管MOSFET器件栅极的方法包括图案化和蚀刻栅极材料的台面。在台面上形成电介质层，并使用化学机械抛光（CMP）进行平面化。有源栅极尺寸被图案化和蚀刻以形成向下延伸到MOSFET栅极两侧的有源区域的源阱和漏极阱。在一个另外的实施例中，孔用金属填充并且金属被平坦化。在一个实施例中，MOSFET器件包括与有源栅极等间隔开的源阱和漏极阱。

66. 发明授权

US5471948A Method of making a compound semiconductor having metallic inclusions 失效
标题翻译：制造具有金属夹杂物的化合物半导体的方法
公开(公告)号：US5471948A
公开(公告)日：1995-12-05
申请号：US240880
申请日：1994-05-11
申请人： Jeremy Burroughes , Rodney T. Hodgson , David T. McInturff , Michael R. Melloch , Nobuo Otsuka , Paul M. Solomon , Alan C. Warren , Jerry M. Woodall
发明人： Jeremy Burroughes , Rodney T. Hodgson , David T. McInturff , Michael R. Melloch , Nobuo Otsuka , Paul M. Solomon , Alan C. Warren , Jerry M. Woodall
IPC分类号： H01L31/0232 , H01L31/105 , H01L21/20
CPC分类号： H01L31/0232 , H01L31/105
摘要： A doped or undoped photoresponsive material having metallic precipitates, and a PiN photodiode utilizing the material for detecting light having a wavelength of 1.3 micrometers. The PiN photodiode includes a substrate having a first compound semiconductor layer disposed thereon. The PiN photodiode further includes an optically responsive compound semiconductor layer disposed above the first compound semiconductor layer. The optically responsive layer includes a plurality of buried Schottky barriers, each of which is associated with an inclusion within a crystal lattice of a Group III-V material. The PiN device also includes a further compound semiconductor layer disposed above the optically responsive layer. For a transversely illuminated embodiment, waveguiding layers may also be disposed above and below the PiN structure. In one example the optically responsive layer is comprised of GaAs:As. The GaAs:As exhibits a very low room temperature dark current, even under forward bias conditions, and a responsivity to 1.3 micrometer radiation modulated at frequencies greater than 1 GHz.
摘要翻译：具有金属沉淀物的掺杂或未掺杂的光响应材料，以及利用该材料用于检测波长为1.3微米的光的PiN光电二极管。 PiN光电二极管包括其上设置有第一化合物半导体层的基板。 PiN光电二极管还包括设置在第一化合物半导体层上方的光学响应化合物半导体层。光学响应层包括多个埋置的肖特基势垒，其中每个都包含在III-V族材料的晶格内。 PiN器件还包括设置在光学响应层上方的另一化合物半导体层。对于横向照明的实施例，也可以在PiN结构的上方和下方设置波导层。在一个实例中，光响应层由GaAs：As组成。 GaAs：As表现出非常低的室温暗电流，即使在正向偏置条件下，并且对频率大于1 GHz的1.3微米辐射的响应度也是如此。

67. 发明授权

US4616242A Enhancement and depletion mode selection layer for field effect transistor 失效
标题翻译：场效应晶体管的增强和耗尽模式选择层
公开(公告)号：US4616242A
公开(公告)日：1986-10-07
申请号：US731822
申请日：1985-05-08
申请人： Paul M. Solomon , Steven L. Wright
发明人： Paul M. Solomon , Steven L. Wright
IPC分类号： H01L29/812 , H01L21/338 , H01L21/8222 , H01L27/06 , H01L27/082 , H01L27/095 , H01L29/10 , H01L29/778 , H01L29/64 , H01L29/80
CPC分类号： H01L27/0605 , H01L29/1029 , H01L29/1075 , H01L29/7786 , H01L29/7787
摘要： A field effect transistor structure suitable for use in an array of such structures disposed on a common substrate (14) is formed with a source terminal (22), a drain (24) terminal, and a gate terminal (26) upon an upper surface of a semiconductor chip. The chip includes a first layer (18) and a second layer (20), the first layer being grown epitaxially upon the second layer. The first layer forms a part of the gate terminal and the second layer includes a charge conduction channel coupling the source region and the drain region. A pocket layer (16) is disposed in the second layer beneath the terminals of the transistor structure and is doped with either an donor dopant or an acceptor dopant for altering the electric field at the conduction channel to insert electrons or remove electrons therefrom so as to convert an operating mode from either an enhancement mode to a depletion mode or from a depletion mode to an enchancement mode. A substrate with a terminal on the backside thereof may be placed contiguous the bottom of said second layer, the back terminal being applied to a negative source of voltage for a transistor structure of n-channel format. The semiconductor material of the chip is a obtained from compounds of elements of the groups III and V of the periodic table.
摘要翻译：适用于布置在公共衬底（14）上的这种结构阵列中的场效应晶体管结构形成有源极端子（22），漏极（24）端子和栅极端子（26）的半导体芯片。芯片包括第一层（18）和第二层（20），第一层在第二层上外延生长。第一层形成栅极端子的一部分，第二层包括耦合源极区和漏极区的电荷传导沟道。袋状层（16）设置在晶体管结构的端子下方的第二层中，并且掺杂有施主掺杂剂或受体掺杂剂，用于改变导电沟道处的电场以插入电子或从其中去除电子，以便将操作模式从增强模式转换为耗尽模式或从耗尽模式转换到增强模式。在其背面具有端子的衬底可以邻近所述第二层的底部放置，所述后端子被施加到用于n沟道格式的晶体管结构的负电压源。芯片的半导体材料是从元素周期表第III族和第Ⅴ族元素的化合物得到的。

68. 发明授权

US08796735B2 Fabrication of a vertical heterojunction tunnel-FET 有权
标题翻译：垂直异质结隧道FET的制造
公开(公告)号：US08796735B2
公开(公告)日：2014-08-05
申请号：US13430041
申请日：2012-03-26
申请人： Isaac Lauer , Amlan Majumdar , Paul M. Solomon , Steven J. Koester
发明人： Isaac Lauer , Amlan Majumdar , Paul M. Solomon , Steven J. Koester
IPC分类号： H01L29/66 , H01L21/336 , H01L29/165 , H01L29/739
CPC分类号： H01L29/165 , H01L29/7391
摘要： Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.
摘要翻译：示例性实施例包括用于制造异质结隧道场效应晶体管（FET）的方法，所述方法包括在绝缘体上硅（SOI）衬底的硅层上形成栅区，在硅层上形成漏极区邻近所述栅极区域并形成与所述栅极区域相邻的垂直异质结源区域，其中所述垂直异质结源区域产生与所述栅极区域相关联的栅极场列的隧道路径。

69. 发明申请

US20140042385A1 CONTACTS-FIRST SELF-ALIGNED CARBON NANOTUBE TRANSISTOR WITH GATE-ALL-AROUND 有权
标题翻译：连接第一个自对准碳纳米管晶体管
公开(公告)号：US20140042385A1
公开(公告)日：2014-02-13
申请号：US13587508
申请日：2012-08-16
申请人： Aaron D. Franklin , Shu-jen Han , Joshua T. Smith , Paul M. Solomon
发明人： Aaron D. Franklin , Shu-jen Han , Joshua T. Smith , Paul M. Solomon
IPC分类号： H01L29/08 , B82Y99/00
CPC分类号： B82Y40/00 , B82Y10/00 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L51/0048 , H01L51/055 , H01L51/0558
摘要： A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed.
摘要翻译：公开了制造半导体器件的方法。碳纳米管沉积在半导体器件的衬底上。在碳纳米管上的衬底上的第一接触。在碳纳米管上的衬底上的第二接触，其中第二接触件通过间隙与第一接触件分离。第一触点和第二触点之间的间隙中的基板的一部分被去除。

70. 发明授权

US08614436B2 Solid state klystron 有权
标题翻译：固态速调管
公开(公告)号：US08614436B2
公开(公告)日：2013-12-24
申请号：US13603110
申请日：2012-09-04
申请人： Paul M. Solomon
发明人： Paul M. Solomon
IPC分类号： H01L29/06
CPC分类号： H01J25/10 , B82Y10/00
摘要： A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.
摘要翻译：通过在导线的两端形成源极接触和漏极接触并且在导线上形成偏置栅极和信号栅极来制造固态速调管结构。导线可以是至少一个碳纳米管或具有长的弹道平均自由路径的至少一个半导体线。通过以对应于信号栅极的相邻指状物之间的弹道载体的渡越时间的整数倍的频率施加信号，载流子在导线内聚束，从而以一定频率放大通过固态速调管的电流信号到信号门，从而实现功率增益。

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