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61. 发明申请

US20120126337A1 SOURCE/DRAIN-TO-SOURCE/DRAIN RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME 有权
标题翻译：来源/排泄源/排水压痕带及其制造方法
公开(公告)号：US20120126337A1
公开(公告)日：2012-05-24
申请号：US12949888
申请日：2010-11-19
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/823418 , H01L21/823475
摘要： A structure and a method of making the structure. The structure includes first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the second semiconductor region; a trench contained in the region of trench isolation and between and abutting the first and second semiconductor regions; and an electrically conductive strap in the trench, the strap electrically connecting the first and second semiconductor regions.
摘要翻译：制作结构的结构和方法。该结构包括半导体衬底中的第一和第二半导体区域，并由半导体衬底中的沟槽隔离区域分隔开; 在所述第一半导体区域上延伸的第一栅电极; 在所述第二半导体区域上延伸的第二栅电极; 包含在沟槽隔离区域中并在第一和第二半导体区域之间并邻接的沟槽; 以及沟槽中的导电带，所述带电连接第一和第二半导体区域。

62. 发明申请

US20120112287A1 GATE-TO-GATE RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME 有权
标题翻译：门到门盖带及其制造方法
公开(公告)号：US20120112287A1
公开(公告)日：2012-05-10
申请号：US12940210
申请日：2010-11-05
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823481 , H01L21/823425 , H01L21/823437
摘要： A structure and methods of making the structure. The structure includes: first and a second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the substrate; a first gate electrode extending over the first semiconductor region and the region of the trench isolation; a second gate electrode extending over the second silicon region and the region of the trench isolation; a trench in the trench isolation; and a strap in the trench connecting the first and second gate electrodes.
摘要翻译：制作结构的方法和结构。该结构包括：半导体衬底中的第一和第二半导体区域，并由衬底中的沟槽隔离区域分隔开; 在所述第一半导体区域上延伸的第一栅电极和所述沟槽隔离区域; 在所述第二硅区域上延伸的第二栅极电极和所述沟槽隔离区域; 沟槽沟槽隔离; 以及连接第一和第二栅电极的沟槽中的带子。

63. 发明申请

US20120104538A1 DAMASCENE METHOD OF FORMING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURE WITH MULTIPLE FIN-SHAPED CHANNEL REGIONS HAVING DIFFERENT WIDTHS 有权
公开(公告)号：US20120104538A1
公开(公告)日：2012-05-03
申请号：US12915463
申请日：2010-10-29
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/02 , H01L21/70
CPC分类号： H01L29/66795 , H01L29/785
摘要： Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET.

64. 发明申请

US20120070064A1 METHOD FOR DETERMINING MASK OPERATION ACTIVITIES 有权
标题翻译：确定掩蔽操作活动的方法
公开(公告)号：US20120070064A1
公开(公告)日：2012-03-22
申请号：US12887565
申请日：2010-09-22
申请人： Emily E. Gallagher , Jed H. Rankin , Alan E. Rosenbluth
发明人： Emily E. Gallagher , Jed H. Rankin , Alan E. Rosenbluth
IPC分类号： G06K9/46
CPC分类号： G03F1/70
摘要： A method and system arrangement for controlling and determining mask operation activities. Upon obtaining chip physical layout design data and running resolution enhancement technology on the chip physical layout design to generate mask features which may include any sub-resolution assist features, a placement sensitivity metric is determined for each of the generated mask features or edge fragments. In one alternative embodiment an edge placement sensitivity metric is determined for each edge of the generated mask features or edge fragments. The determined sensitivity metrics for each feature are classified and applied to subsequent mask operational activities such as post processing, write exposure and mask repair. The types of decisions based on the sensitivity metric may include minimizing or maximizing OPC processing; e-beam exposure adjustment in mask write; and selection of which mask features to repair as well as what repair criteria to then apply, and adjusting quality requirement criteria for manufacturing assessment.
摘要翻译：一种用于控制和确定面罩操作活动的方法和系统布置。在芯片物理布局设计上获得芯片物理布局设计数据和运行分辨率增强技术以产生可包括任何子分辨率辅助特征的掩模特征时，为每个生成的掩模特征或边缘片段确定放置灵敏度度量。在一个替代实施例中，为所生成的掩模特征或边缘片段的每个边缘确定边缘放置灵敏度度量。所确定的每个特征的灵敏度度量被分类并应用于随后的掩模操作活动，例如后处理，写入曝光和掩模修复。基于灵敏度度量的决策类型可以包括最小化或最大化OPC处理; 掩模写入中的电子束曝光调整; 并选择要修复的掩模特征以及哪些修复标准，然后适用，并调整制造评估的质量要求标准。

65. 发明申请

US20120056264A1 METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET 有权
标题翻译：用于形成和结构的用于大量生长的源/排水带的方法
公开(公告)号：US20120056264A1
公开(公告)日：2012-03-08
申请号：US12876343
申请日：2010-09-07
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer, relative to a bottom of the structure. Each of the fins comprises a central semiconductor portion and conductive end portions. At least one conductive strap may be positioned within the insulator layer below the fins, relative to the bottom of the structure. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap further includes recessed portions disposed within the insulator layer, below the plurality of fins, relative to the bottom of the structure, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins, relative to the bottom of the structure. The conductive strap is disposed in at least one of a source and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator.
摘要翻译：一种方法和半导体结构包括在衬底上的绝缘体层，相对于该结构的底部在绝缘体层之上的多个平行的鳍。每个翅片包括中心半导体部分和导电端部。至少一个导电带可以相对于结构的底部定位在翅片下方的绝缘体层内。导电带可以垂直于翅片并接触翅片。导电带还包括设置在绝缘体层内的凹陷部分，相对于结构的底部在多个翅片之下，并且在多个翅片中的每一个之间，以及设置在绝缘体层上方的突出部分，多个翅片相对于结构的底部。导电带设置在半导体结构的源极和漏极区域中的至少一个中。栅极绝缘体接触并覆盖翅片的中心半导体部分，并且栅极导体覆盖并接触栅极绝缘体。

66. 发明授权

US08015514B2 Random personalization of chips during fabrication 有权
标题翻译：制造期间芯片的随机个性化
公开(公告)号：US08015514B2
公开(公告)日：2011-09-06
申请号：US12344725
申请日：2008-12-29
申请人： Mark D. Jaffe , Stephen A. Mongeon , Leah M. P. Pastel , Jed H. Rankin
发明人： Mark D. Jaffe , Stephen A. Mongeon , Leah M. P. Pastel , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/66 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.
摘要翻译：公开了用于在制造期间随机个性化芯片的方法的实施例，个性化芯片结构和用于这种个性化芯片结构的设计结构。实施例使用电子设备设计和制造过程来随机地或伪随机地在每个芯片上形成的特定电子设备的一个或多个实例中创建特定变化。调整设备设计和制造过程，使得特定变化以某种预定概率发生，从而产生期望的硬件分布和个性化每个芯片。所得到的个性化芯片可用于芯片的模态分配。例如，当单芯片设计可用于支持多种应用时，芯片可以被个性化以允许排序。所产生的个性化芯片也可以用于随机数生成，用于创建唯一的片上标识符，私钥等。

67. 发明申请

US20110208482A1 Variable Focus Point Lens 有权
标题翻译：可变焦点镜头
公开(公告)号：US20110208482A1
公开(公告)日：2011-08-25
申请号：US12708561
申请日：2010-02-19
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G06F17/50 , G02B3/12
CPC分类号： G02B3/14
摘要： A variable focal point lens includes a transparent tank, which comprises a transparent enclosure containing a transparent flexible membrane separating the inner volume of the transparent tank into an upper tank portion and a lower tank portion. The upper tank portion and the lower tank portion contain liquids having different indices of refraction. The transparent flexible membrane is electrostatically displaced to change the thicknesses of the first tank portion and the second tank portion in the path of the light, thereby shifting the focal point of the lens axially and/or laterally. The electrostatic displacement of the membrane may be effected by a fixed charge in the membrane and an array of enclosure-side conductive structures on the transparent enclosure, or an array of membrane-side conductive structures on the transparent membrane and an array of enclosure-side conductive structures.
摘要翻译：可变焦点透镜包括透明容器，透明容器包括透明的外壳，该透明外壳包含将透明容器的内部容积分隔成上部容器部分和下部容器部分的透明柔性膜。上罐部分和下罐部分含有不同折射率的液体。透明柔性膜被静电移位以改变光路中的第一罐部分和第二罐部分的厚度，从而轴向和/或横向地移动透镜的焦点。膜的静电位移可以通过膜中的固定电荷和透明外壳上的封闭侧导电结构阵列，或透明膜上的膜侧导电结构阵列和外壳侧阵列导电结构。

68. 发明申请

US20110098838A1 SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS 有权
标题翻译：用于校正集成电路芯片的系统参数变化的系统和方法，以最小化电路有限的损失
公开(公告)号：US20110098838A1
公开(公告)日：2011-04-28
申请号：US12603679
申请日：2009-10-22
申请人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.
摘要翻译：公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。存储处理信息和芯片的映射。处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。地图可以指示设备参数中的区域变化（例如，阈值电压）。基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。

69. 发明授权

US07914949B2 Method for testing a photomask 有权
标题翻译：光掩模测试方法
公开(公告)号：US07914949B2
公开(公告)日：2011-03-29
申请号：US10906564
申请日：2005-02-24
申请人： Jed H. Rankin
发明人： Jed H. Rankin
IPC分类号： G03F1/00
CPC分类号： G03F7/7065 , G03F1/84 , G03F7/705
摘要： A method, a recording medium and an apparatus for testing a photomask are provided. In the disclosed method, a particular region of a photomask is selected, either from a physical instance of the photomask, or from the photomask as represented by a digital representation thereof. The particular region is then characterized by identifying a pattern type present in the particular region. A lithographic process stress condition is determined for the particular region, considering the pattern type, and thereafter, a result of lithographically patterning a feature is determined by simulating a photolithographic exposure, using the particular region of the photomask under the lithographic process stress condition. Then, it is decided whether the particular region of the photomask is acceptable based on the result of the simulated exposure only under the lithographic process stress condition.
摘要翻译：提供了一种方法，记录介质和用于测试光掩模的设备。在所公开的方法中，从光掩模的物理实例或由其数字表示所示的光掩模中选择光掩模的特定区域。特定区域的特征在于识别存在于特定区域中的图案类型。考虑到图案类型，确定特定区域的光刻工艺应力条件，此后，通过在光刻工艺应力条件下使用光掩模的特定区域模拟光刻曝光来确定特征的光刻图案的结果。然后，基于仅在光刻工艺应力条件下的模拟曝光的结果，确定光掩模的特定区域是否可接受。

70. 发明授权

US07763531B2 Method and structure to process thick and thin fins and variable fin to fin spacing 有权
标题翻译：处理厚薄翅片和可变翅片翅片间距的方法和结构
公开(公告)号：US07763531B2
公开(公告)日：2010-07-27
申请号：US11846544
申请日：2007-08-29
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthler, Jr. , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthler, Jr. , Jed H. Rankin , William R. Tonti
IPC分类号： H01L21/425
CPC分类号： B07C5/344 , G01R31/2831
摘要： The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FETs.
摘要翻译：本公开描述了在同一衬底上具有多个半导体鳍片的集成电路，其具有不同的宽度和可变间隔。形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET。

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