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1. 发明授权

US08378394B2 Method for forming and structure of a recessed source/drain strap for a MUGFET 有权
标题翻译：用于MUGFET的凹陷源/排水带的形成和结构的方法
公开(公告)号：US08378394B2
公开(公告)日：2013-02-19
申请号：US12876343
申请日：2010-09-07
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/76
CPC分类号： H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer, relative to a bottom of the structure. Each of the fins comprises a central semiconductor portion and conductive end portions. At least one conductive strap may be positioned within the insulator layer below the fins, relative to the bottom of the structure. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap further includes recessed portions disposed within the insulator layer, below the plurality of fins, relative to the bottom of the structure, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins, relative to the bottom of the structure. The conductive strap is disposed in at least one of a source and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator.
摘要翻译：一种方法和半导体结构包括在衬底上的绝缘体层，相对于该结构的底部在绝缘体层之上的多个平行的鳍。每个翅片包括中心半导体部分和导电端部。至少一个导电带可以相对于结构的底部定位在翅片下方的绝缘体层内。导电带可以垂直于翅片并接触翅片。导电带还包括设置在绝缘体层内的凹部，相对于结构的底部在多个散热片的下方，以及设置在绝缘体层之上的每个散热片之间的突出部分，多个翅片相对于结构的底部。导电带设置在半导体结构的源极和漏极区域中的至少一个中。栅极绝缘体接触并覆盖翅片的中心半导体部分，并且栅极导体覆盖并接触栅极绝缘体。

2. 发明授权

US08242561B2 Semiconductor devices with improved self-aligned contact areas 有权
标题翻译：具有改善的自对准接触面积的半导体器件
公开(公告)号：US08242561B2
公开(公告)日：2012-08-14
申请号：US12702684
申请日：2010-02-09
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/786
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： A field effect device includes a channel region disposed on a silicon on insulator (SOI) layer, a gate portion disposed on the channel region, a source region disposed on the SOI layer and connected to the channel region having a horizontal surface and a vertical surface, the vertical surface arranged perpendicular to a linear axis of the device, a silicide portion that includes the horizontal surface and vertical surface of the source region, a contact including a metallic material in contact with the horizontal surface and vertical surface of the source region, and a drain region connected to the channel region disposed on the SOI layer.
摘要翻译：场效应器件包括设置在绝缘体上硅（SOI）层上的沟道区域，设置在沟道区上的栅极部分，设置在SOI层上的源极区域，并连接到具有水平表面和垂直表面的沟道区域垂直于装置的线性轴排列的垂直表面，包括源区域的水平表面和垂直表面的硅化物部分，包括与源区域的水平表面和垂直表面接触的金属材料的触点，以及连接到设置在SOI层上的沟道区的漏极区。

3. 发明申请

US20120056264A1 METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET 有权
标题翻译：用于形成和结构的用于大量生长的源/排水带的方法
公开(公告)号：US20120056264A1
公开(公告)日：2012-03-08
申请号：US12876343
申请日：2010-09-07
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer, relative to a bottom of the structure. Each of the fins comprises a central semiconductor portion and conductive end portions. At least one conductive strap may be positioned within the insulator layer below the fins, relative to the bottom of the structure. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap further includes recessed portions disposed within the insulator layer, below the plurality of fins, relative to the bottom of the structure, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins, relative to the bottom of the structure. The conductive strap is disposed in at least one of a source and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator.
摘要翻译：一种方法和半导体结构包括在衬底上的绝缘体层，相对于该结构的底部在绝缘体层之上的多个平行的鳍。每个翅片包括中心半导体部分和导电端部。至少一个导电带可以相对于结构的底部定位在翅片下方的绝缘体层内。导电带可以垂直于翅片并接触翅片。导电带还包括设置在绝缘体层内的凹陷部分，相对于结构的底部在多个翅片之下，并且在多个翅片中的每一个之间，以及设置在绝缘体层上方的突出部分，多个翅片相对于结构的底部。导电带设置在半导体结构的源极和漏极区域中的至少一个中。栅极绝缘体接触并覆盖翅片的中心半导体部分，并且栅极导体覆盖并接触栅极绝缘体。

4. 发明授权

US09064974B2 Barrier trench structure and methods of manufacture 有权
标题翻译：阻隔沟槽结构和制造方法
公开(公告)号：US09064974B2
公开(公告)日：2015-06-23
申请号：US13108144
申请日：2011-05-16
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/092 , H01L21/84 , H01L21/762 , H01L27/12 , H01L21/8234
CPC分类号： H01L27/092 , H01L21/76283 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/0642
摘要： A method includes forming at least one shallow trench isolation structure in a substrate to isolate adjacent different type devices. The method further includes forming a barrier trench structure in the substrate to isolate diffusions of adjacent same type devices. The method further includes spanning the barrier trench structure with material to connect the diffusions of the adjacent same type device, on a same level as the adjacent same type devices.
摘要翻译：一种方法包括在衬底中形成至少一个浅沟槽隔离结构以隔离相邻的不同类型的器件。该方法还包括在衬底中形成阻挡沟槽结构以隔离相邻相同类型器件的扩散。该方法进一步包括将阻挡沟槽结构与材料连接，以将相邻相同类型器件的扩散连接在与相邻相同类型器件相同的水平上。

5. 发明授权

US07971158B2 Spacer fill structure, method and design structure for reducing device variation 失效
标题翻译：间隔填充结构，减少装置变化的方法和设计结构
公开(公告)号：US07971158B2
公开(公告)日：2011-06-28
申请号：US12144004
申请日：2008-06-23
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.
摘要翻译：提供了用于间隔物填充结构的设计结构，并且更具体地，提供了间隔件填充结构，制造方法和用于减小装置变化的设计结构。该结构包括在器件的不同区域中的多个虚拟填充形状，其被配置为使得栅极周边与栅极面积比将导致芯片上的总周长密度是均匀的。

6. 发明申请

US20090319973A1 SPACER FILL STRUCTURE, METHOD AND DESIGN STRUCTURE FOR REDUCING DEVICE VARIATION 失效
标题翻译：隔膜填充结构，减少设备变化的方法和设计结构
公开(公告)号：US20090319973A1
公开(公告)日：2009-12-24
申请号：US12144004
申请日：2008-06-23
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： G06F17/50 , H01L21/00
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.
摘要翻译：提供了用于间隔物填充结构的设计结构，并且更具体地，提供了间隔件填充结构，制造方法和用于减小装置变化的设计结构。该结构包括在器件的不同区域中的多个虚拟填充形状，其被配置为使得栅极周边与栅极面积比将导致芯片上的总周长密度是均匀的。

7. 发明授权

US06947275B1 Fin capacitor 失效
标题翻译：散热片电容
公开(公告)号：US06947275B1
公开(公告)日：2005-09-20
申请号：US10711975
申请日：2004-10-18
申请人： Brent A Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01G4/005 , H01G4/012 , H01G4/06 , H01G4/33 , H01L21/02 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/13
CPC分类号： H01G4/012 , H01G4/06 , H01G4/33 , H01L21/84 , H01L27/1085 , H01L27/13 , H01L28/92 , Y10T29/435
摘要： Disclosed is a capacitor structure and method for forming the same. This structure has a conductive substrate, conductive fins extending above the substrate, and trenches extending into the substrate. These trenches are positioned between locations where the fins extend above the substrate. The invention includes an insulator in the trenches and covering the fins. This insulator separates the substrate and fins from a conductive top plate that covers the fins and fills the trenches. A bottom plate contact electrically connects the fins and the substrate such that the fins and the substrate comprise a bottom plate of the capacitor structure.
摘要翻译：公开了一种电容器结构及其形成方法。该结构具有导电基板，在基板上方延伸的导电翅片和延伸到基板中的沟槽。这些沟槽位于翅片在衬底上方延伸的位置之间。本发明包括沟槽中的绝缘体并覆盖翅片。该绝缘体将基板和散热片与覆盖翅片的导电顶板隔开并填充沟槽。底板接触件电连接散热片和基板，使得散热片和基板包括电容器结构的底板。

8. 发明授权

US06646305B2 Grounded body SOI SRAM cell 有权
标题翻译：接地体SOI SRAM单元
公开(公告)号：US06646305B2
公开(公告)日：2003-11-11
申请号：US09915061
申请日：2001-07-25
申请人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
发明人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L27/1104
摘要： A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.
摘要翻译：一种半导体存储器件，包括：在衬底绝缘体的顶部上具有薄硅层的SOI衬底; 以及包括四个NFET和位于薄硅层中的两个PFET的SRAM，每个NFET和PFET具有在源极区域和漏极区域之间的主体区域，其中两个NFET的主体电连接到地。另外，两个PFET的主体电连接到VDD。

9. 发明授权

US07075153B2 Grounded body SOI SRAM cell 有权
标题翻译：接地体SOI SRAM单元
公开(公告)号：US07075153B2
公开(公告)日：2006-07-11
申请号：US10640807
申请日：2003-08-14
申请人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
发明人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/1203 , H01L27/1104
摘要： A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.
摘要翻译：一种半导体存储器件，包括：在衬底绝缘体的顶部上具有薄硅层的SOI衬底; 以及包括四个NFET和位于薄硅层中的两个PFET的SRAM，每个NFET和PFET具有在源极区域和漏极区域之间的主体区域，其中两个NFET的主体电连接到地。另外，两个PFET的主体电连接到V DD。

10. 发明授权

US06940130B2 Body contact MOSFET 失效
标题翻译：体接触MOSFET
公开(公告)号：US06940130B2
公开(公告)日：2005-09-06
申请号：US10687333
申请日：2003-10-16
申请人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
发明人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
摘要翻译：公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

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