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61. 发明授权

US06383906B1 Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption 有权
标题翻译：在具有超低硅消耗的半导体晶片中形成结漏电的金属硅化物的方法
公开(公告)号：US06383906B1
公开(公告)日：2002-05-07
申请号：US09641436
申请日：2000-08-18
申请人： Karsten Wieczorek , Nicholas Kepler , Paul R. Besser , Larry Y. Wang
发明人： Karsten Wieczorek , Nicholas Kepler , Paul R. Besser , Larry Y. Wang
IPC分类号： H01L214763
CPC分类号： H01L29/6653 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method for forming ultra shallow junctions in a semiconductor wafer uses disposable spacers and a silicon cap layer to achieve ultra-low low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of a semiconductor device. Silicon nitride disposable spacers are formed over the metal layer in the region of the sidewall spacers previously formed on the sidewalls of the gate. A silicon cap layer is deposited over the metal layer and the disposable spacers. Rapid thermal annealing is performed to form the high-ohmic phase of the salicide, with the disposable spacers preventing interaction and between the cobalt and the silicon in the area between the gate and the source/drain junctions along the sidewall spacers. The silicon cap layer provides a source of silicon for consumption during the first phase of salicide formation, reducing the amount of silicon of the source/drain junctions that is consumed.
摘要翻译：在半导体晶片中形成超浅结的方法使用一次性间隔物和硅帽层，以在自对准硅化物形成过程中实现超低的低硅消耗。难熔金属层，例如钴层，沉积在半导体器件的栅极和源极/漏极结上。氮化硅一次性间隔物形成在预先形成在栅极的侧壁上的侧壁间隔区域中的金属层的上方。在金属层和一次性间隔物上沉积硅覆盖层。进行快速热退火以形成硅化物的高欧姆相，其中一次性间隔物防止了沿着侧壁间隔物的栅极和源极/漏极结之间的区域中的钴和硅之间的相互作用。硅封层在硅化物形成的第一阶段期间提供硅消耗源，从而减少消耗的源极/漏极结的硅量。

62. 发明授权

US06271122B1 Method of compensating for material loss in a metal silicone layer in contacts of integrated circuit devices 有权
标题翻译：补偿集成电路器件触点中金属硅胶层材料损耗的方法
公开(公告)号：US06271122B1
公开(公告)日：2001-08-07
申请号：US09351756
申请日：1999-07-12
申请人： Karsten Wieczorek , Michael Raab , Gert Burbach
发明人： Karsten Wieczorek , Michael Raab , Gert Burbach
IPC分类号： H01L214763
CPC分类号： H01L21/76856 , H01L21/28518 , H01L21/76843 , H01L21/76846 , H01L21/76855
摘要： There is provided a semiconductor device comprising, for example, a MOS structure having a low electrical resistance in contacts and local interconnects, and a method for fabricating the device. When openings are formed in a dielectric region of a MOS structure, the thin metal silicide layer on top of a drain/source region is diminished due to the limited selectivity of the etch process and the need to over-etch to obtain appropriate electrical contacts. Consequently, the contact resistance is increased resulting in an increased contact resistance. Therefore, a bilayer metal is deposited on the metal silicide layer and the surface of the openings, wherein the metal layer that is in contact with the metal silicide layer is preferably the same metal as the metal of the metal silicide layer. In a subsequent annealing process, the metal of the bilayer partially converts into metal silicide, thereby increasing the initial metal silicide layer and concurrently reducing the contact resistance.
摘要翻译：提供了一种半导体器件，其包括例如在触点和局部互连中具有低电阻的MOS结构以及该器件的制造方法。当在MOS结构的电介质区域中形成开口时，由于蚀刻工艺的选择性受限以及过度蚀刻以获得适当的电接触的需要，漏极/源极区域顶部的金属硅化物层减小。因此，接触电阻增加，导致接触电阻增加。因此，在金属硅化物层和开口表面上沉积双层金属，其中与金属硅化物层接触的金属层优选与金属硅化物层的金属相同的金属。在随后的退火工艺中，双层金属部分地转变为金属硅化物，从而增加初始金属硅化物层并同时降低接触电阻。

63. 发明申请

US20080081471A1 TECHNIQUE FOR LOCALLY ADAPTING TRANSISTOR CHARACTERISTICS BY USING ADVANCED LASER/FLASH ANNEAL TECHNIQUES 有权
标题翻译：使用先进激光/闪光技术的局部适应晶体管特性的技术
公开(公告)号：US20080081471A1
公开(公告)日：2008-04-03
申请号：US11736939
申请日：2007-04-18
申请人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
发明人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
IPC分类号： H01L21/44
CPC分类号： H01L21/268 , H01L21/823807 , H01L27/11 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.
摘要翻译：通过对诸如硅化镍之类的金属硅化物形成进行诸如激光退火，闪光退火等复杂的退火技术，可以显着地减少诸如SRAM通孔之类的敏感器件区域中的硅化镍缺陷的风险。此外，可以以高度局部化的方式执行掺杂剂的激活，使得当激活和再结晶漏极和源极区域时，可以避免栅极绝缘层的过度损坏。

64. 发明申请

US20060244069A1 Semiconductor device having a gate dielectric of different blocking characteristics 审中-公开
标题翻译：具有不同阻挡特性的栅电介质的半导体器件
公开(公告)号：US20060244069A1
公开(公告)日：2006-11-02
申请号：US11284270
申请日：2005-11-21
申请人： Karsten Wieczorek , Michael Raab , Karla Romero
发明人： Karsten Wieczorek , Michael Raab , Karla Romero
IPC分类号： H01L27/12
CPC分类号： H01L29/518 , H01L21/28185 , H01L21/28202 , H01L21/2822 , H01L21/823462 , H01L21/823857 , H01L21/84 , H01L29/4908
摘要： By locally adapting the blocking capability of gate insulation layers for N-channel transistors and P-channel transistors, the reliability and threshold stability of the P-channel transistor may be enhanced, while nevertheless electron mobility of the N-channel transistor may be kept at a high level. This may be accomplished by incorporating a different amount of a dielectric dopant into respective gate insulation layer portions.
摘要翻译：通过局部地适应N沟道晶体管和P沟道晶体管的栅极绝缘层的阻挡能力，可以提高P沟道晶体管的可靠性和阈值稳定性，而N沟道晶体管的电子迁移率可以保持在高水平这可以通过将不同量的电介质掺杂剂并入相应的栅极绝缘层部分来实现。

65. 发明申请

US20050070082A1 Semiconductor device having a nickel/cobalt silicide region formed in a silicon region 审中-公开
标题翻译：具有形成在硅区域中的镍/钴硅化物区域的半导体器件
公开(公告)号：US20050070082A1
公开(公告)日：2005-03-31
申请号：US10859552
申请日：2004-06-02
申请人： Thorsten Kammler , Karsten Wieczorek , Austin Frenkel
发明人： Thorsten Kammler , Karsten Wieczorek , Austin Frenkel
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： By forming a buried nickel silicide layer followed by a cobalt silicide layer in silicon-containing regions, such as a gate electrode of a field effect transistor, the superior characteristics of both silicides may be combined so as to provide the potential for further device scaling without unduly compromising the sheet resistance and the contact resistance of scaled silicon circuit features.
摘要翻译：通过在含硅区域（例如场效应晶体管的栅电极）中形成掩埋的硅化镍层和硅化钴层之后，可以组合两种硅化物的优异特性，从而为进一步的器件成形提供潜力，而无需不适当地损害了尺寸硅电路特征的薄层电阻和接触电阻。

66. 发明授权

US06806126B1 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US06806126B1
公开(公告)日：2004-10-19
申请号：US10236200
申请日：2002-09-06
申请人： Scott Luning , Karsten Wieczorek , Thorsten Kammler
发明人： Scott Luning , Karsten Wieczorek , Thorsten Kammler
IPC分类号： H01L21338
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/7833 , Y10S257/90
摘要： An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).
摘要翻译：一种具有降低的栅极电阻的绝缘栅极半导体器件（100）和用于制造半导体器件（100）的方法。栅极结构（112）形成在半导体衬底（102）的主表面（104）上。在栅极结构（112）的侧壁附近形成连续的氮化物间隔物（118,128）。使用单个蚀刻来蚀刻和凹入氮化物间隔物（118,128）以暴露栅极结构（112）的上部（115A，117A）。源极（132）和漏极（134）区域形成在半导体衬底（102）中。在栅极结构（112）和源极区（132）和漏极区（134）的顶表面（109）和暴露的上部（115A，117A）上形成硅化物区域（140,142,144）。电极（150,152,154）形成为与相应的栅极结构（112），源极区（132）和漏极区（134）的硅化物（140,142,144）接触。

67. 发明授权

US06746927B2 Semiconductor device having a polysilicon line structure with increased metal silicide portions and method for forming the polysilicon line structure of a semiconductor device 有权
公开(公告)号：US06746927B2
公开(公告)日：2004-06-08
申请号：US10422492
申请日：2003-04-24
申请人： Thorsten Kammler , Karsten Wieczorek , Christof Streck
发明人： Thorsten Kammler , Karsten Wieczorek , Christof Streck
IPC分类号： H01L21336
CPC分类号： H01L21/28052 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method is provided for forming polysilicon line structures, such as gate electrodes of field effect transistors, according to which oxide spacers are removed from the sidewalls of the poly gate lines before depositing the liner oxide. Accordingly, after formation of the final spacers, the polysilicon line sidewalls are no longer covered with spacer oxide but all silicide pre-cleans can clear the poly sidewalls completely which thus leads to improved silicidation conditions, resulting in gate lines exhibiting very low sheet resistivity.

68. 发明授权

US06306698B1 Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same 有权
标题翻译：具有栅电极和源/漏区以上的不同厚度的金属硅化物区域的半导体器件及其制造方法
公开(公告)号：US06306698B1
公开(公告)日：2001-10-23
申请号：US09558963
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L21336
CPC分类号： H01L29/66507
摘要： The present invention is directed to a semiconductor device (100) having enhanced electrical performance characteristics, and a method of making such a device. In one illustrative embodiment, the semiconductor device (100) is comprised of a polysilicon gate electrode (104) positioned above a gate insulation layer (105), a plurality of source/drain regions (109) formed in a semiconducting substrate (101), a first metal silicide region (111A) positioned above the gate electrode (104), a second metal silicide region (107) positioned above each of the source/drain regions (109), wherein the first metal silicide region (111A) is approximately 2-10 times thicker than each of the second metal silicide regions (107). In one illustrative embodiment, the inventive method disclosed herein comprises forming a first layer of a refractory metal (110) above a layer of polysilicon (104), and converting the refractory metal layer (110) to a metal suicide layer (111), and patterning the metal silicide layer (111) and the gate electrode layer (104) to form a metal silicide region (111A) above the gate electrode (104). The method further comprises forming a plurality of source/drain regions (109) in the substrate (101), forming a second layer comprised of a refractory metal above at least the gate stack (122) and the source/drain regions (109). The method concludes with converting at least a portion of the second layer of refractory metal to a second metal silicide region above each of the source/drain regions (109).
摘要翻译：本发明涉及具有增强的电气性能特性的半导体器件（100）以及制造这种器件的方法。在一个说明性实施例中，半导体器件（100）由位于栅极绝缘层（105）上方的多晶硅栅电极（104），形成在半导体衬底（101）中的多个源极/漏极区域（109）位于栅电极（104）上方的第一金属硅化物区（111A），位于源极/漏极区（109）之上的第二金属硅化物区（107），其中第一金属硅化物区（111A）约为2 比第二金属硅化物区域（107）的厚度大10〜10倍。在一个示例性实施例中，本文公开的本发明的方法包括在多晶硅层（104）上方形成难熔金属（110）的第一层，并将难熔金属层（110）转化为金属硅化物层（111），以及图案化金属硅化物层（111）和栅电极层（104）以在栅电极（104）上方形成金属硅化物区域（111A）。该方法还包括在衬底（101）中形成多个源极/漏极区（109），在至少栅极堆叠（122）和源极/漏极区（109）之上形成由难熔金属组成的第二层。该方法的结论是将难熔金属的第二层的至少一部分转换成源极/漏极区域（109）之上的第二金属硅化物区域。

69. 发明授权

US06204177B1 Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal 有权
$Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal$
标题翻译：通过合金化难熔金属在半导体晶片中形成结无漏电金属硅化物的方法
公开(公告)号：US06204177B1
公开(公告)日：2001-03-20
申请号：US09185515
申请日：1998-11-04
申请人： Paul R. Besser , Nick Kepler , Karsten Wieczorek
发明人： Paul R. Besser , Nick Kepler , Karsten Wieczorek
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/456 , H01L29/4933
摘要： A method of forming metal silicide in a semiconductor wafer with reduced junction leakage introduces an alloy at cobalt grain boundaries within a cobalt layer that overlays a silicon layer. The alloy element can be precipitated during deposition of the cobalt and the alloy element, or by an intermediate anneal after deposition. The cobalt layer and the silicon layer are then annealed to form metal silicide regions. By precipitating an alloy at the cobalt grain boundaries, cobalt diffusion at the grain boundaries is retarded during a first rapid thermal annealing step. Bulk diffusion is encouraged, and a more uniform silicide film with reduced interface roughness is produced. Since the interface roughness is reduced with the methods of the present invention, junction leakage is reduced. This allows shallower junctions to be fabricated, leading to devices with improved performance.
摘要翻译：在具有减少的结漏电的半导体晶片中形成金属硅化物的方法在覆盖硅层的钴层内的钴晶界处引入合金。在钴和合金元素的沉积期间，或者通过沉积后的中间退火，合金元素可以沉淀。然后将钴层和硅层退火以形成金属硅化物区域。通过在钴晶界析出合金，在第一快速热退火步骤期间，在晶界处的钴扩散被延迟。鼓励扩散，并产生具有降低的界面粗糙度的更均匀的硅化物膜。由于通过本发明的方法减小了界面粗糙度，所以结漏电减少。这允许制造较浅的结，导致具有改进性能的器件。

70. 发明授权

US6165903A Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation 有权
标题翻译：在具有沉积硅层的半导体晶片中形成超浅结的方法，以减少在水化过程中的硅消耗
公开(公告)号：US6165903A
公开(公告)日：2000-12-26
申请号：US185516
申请日：1998-11-04
申请人： Paul R. Besser , Nick Kepler , Karsten Wieczorek
发明人： Paul R. Besser , Nick Kepler , Karsten Wieczorek
IPC分类号： H01L21/285 , H01L21/44
CPC分类号： H01L21/28525 , H01L21/28518
摘要： A method for forming ultra shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high resistivity metal silicide regions are formed on the gate and source/drain junctions. Silicon is then deposited in a layer on the high resistivity metal silicide regions. An annealing step is then performed to form low resistivity metal silicide regions on the gate and source/drain junctions. The deposited silicon is a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide (such as CoSi) to a low resistivity metal silicide (such as CoSi.sub.2). Since the additional silicon provided in the deposited layer is consumed, there is reduced consumption of the silicon from the ultra-shallow junctions, thereby preventing the bottom of the silicide regions from reaching the bottom of the source/drain junctions.
摘要翻译：用于在半衰期期间形成超浅结的方法，其中在硅化过程中硅消耗减少，在硫化过程中提供额外的硅。在半导体器件中形成栅极和源极/漏极结之后，在栅极和源极/漏极结上形成高电阻金属硅化物区域。然后将硅沉积在高电阻率金属硅化物区域上的层中。然后执行退火步骤以在栅极和源极/漏极结上形成低电阻率金属硅化物区域。沉积的硅是在将高电阻率金属硅化物（例如CoSi）转变成低电阻率金属硅化物（例如CoSi 2）期间用作扩散物质的硅源。由于在沉积层中提供的附加硅被消耗，所以硅从超浅结的消耗减少，从而防止硅化物区的底部到达源极/漏极结的底部。

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