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61. 发明授权

US08525292B2 SOI device with DTI and STI 有权
标题翻译：具有DTI和STI的SOI器件
公开(公告)号：US08525292B2
公开(公告)日：2013-09-03
申请号：US13088376
申请日：2011-04-17
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/00
CPC分类号： H01L21/76229 , H01L21/743 , H01L21/76232 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： An SOI structure including a semiconductor on insulator (SOI) substrate including a top silicon layer, an intermediate buried oxide (BOX) layer and a bottom substrate; at least two wells in the bottom substrate; a deep trench isolation (DTI) separating the two wells, the DTI having a top portion extending through the BOX layer and top silicon layer and a bottom portion within the bottom substrate wherein the bottom portion has a width that is larger than a width of the top portion; and at least two semiconductor devices in the silicon layer located over one of the wells, the at least two semiconductor devices being separated by a shallow trench isolation within the top silicon layer.
摘要翻译：包括绝缘体上半导体（SOI）衬底的SOI结构，包括顶部硅层，中间掩埋氧化物（BOX）层和底部衬底; 底部底物中至少有两口井; 分离两个阱的深沟槽隔离（DTI），DTI具有延伸穿过BOX层和顶部硅层的顶部和底部衬底内的底部部分，其中底部部分的宽度大于顶部以及位于所述阱之一上的所述硅层中的至少两个半导体器件，所述至少两个半导体器件由所述顶部硅层内的浅沟槽隔离隔开。

62. 发明授权

US08513765B2 Formation method and structure for a well-controlled metallic source/drain semiconductor device 有权
标题翻译：良好控制的金属源/漏极半导体器件的形成方法和结构
公开(公告)号：US08513765B2
公开(公告)日：2013-08-20
申请号：US12838844
申请日：2010-07-19
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/02
CPC分类号： H01L29/7839 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/66795
摘要： A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.
摘要翻译：用于形成半导体器件的器件和方法包括在与栅极结构相邻的沟道层上生长凸起的半导体区域。在凸起的半导体区域和栅极结构之间形成空间。在至少凸起的半导体区域上沉积金属层。凸起的半导体区域被硅化以在通道层中形成硅化物，该沟道层在对应于空间的位置处更深地延伸到沟道层中。

63. 发明授权

US08492839B2 Same-chip multicharacteristic semiconductor structures 有权
标题翻译：同芯片多特征半导体结构
公开(公告)号：US08492839B2
公开(公告)日：2013-07-23
申请号：US12861976
申请日：2010-08-24
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L27/1211 , H01L27/1203
摘要： In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.
摘要翻译：在一个示例性实施例中，半导体结构包括：绝缘体上半导体衬底，具有覆盖绝缘层的顶部半导体层，绝缘层覆盖在底部衬底层上; 至少一个第一装置至少部分地覆盖并设置在顶部半导体层的第一部分上，其中第一部分具有第一厚度，第一宽度和第一深度; 以及至少一个第二装置，其至少部分地覆盖并设置在顶部半导体层的第二部分上，其中第二部分具有第二厚度，第二宽度和第二深度，其中以下至少一个成立：第一厚度大于第二厚度，第一宽度大于第二宽度，第一深度大于第二深度。

64. 发明授权

US08445971B2 Field effect transistor device with raised active regions 有权
标题翻译：场效应晶体管器件具有凸起的有源区
公开(公告)号：US08445971B2
公开(公告)日：2013-05-21
申请号：US13237319
申请日：2011-09-20
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/41783 , H01L29/165 , H01L29/41775 , H01L29/66628 , H01L29/66772 , H01L29/78654
摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.
摘要翻译：一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面，第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。

65. 发明授权

US08435846B2 Semiconductor devices with raised extensions 有权
标题翻译：具有凸起延伸的半导体器件
公开(公告)号：US08435846B2
公开(公告)日：2013-05-07
申请号：US13251757
申请日：2011-10-03
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/336 , H01L21/461 , H01L29/76 , H01L29/66
CPC分类号： H01L29/4983 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7834
摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.
摘要翻译：公开了晶体管器件及其制造方法。在一种方法中，在基板上形成虚拟栅极结构。虚拟门结构的底部是底切的。此外，在基板上形成阶梯状，凸起的源极和漏极区域，以及由底切形成的至少一个底切部。去除虚拟栅极结构并在衬底上形成替换栅极。

66. 发明授权

US08394710B2 Semiconductor devices fabricated by doped material layer as dopant source 有权
标题翻译：由掺杂材料层制造的半导体器件作为掺杂剂源
公开(公告)号：US08394710B2
公开(公告)日：2013-03-12
申请号：US12819440
申请日：2010-06-21
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/2254 , H01L21/2255 , H01L21/2257 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L21/845 , H01L27/1211 , H01L29/165 , H01L29/42392 , H01L29/66439 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/66803 , H01L29/775 , H01L29/78 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L29/78696
摘要： A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.
摘要翻译：提供一种形成半导体器件的方法，其中用于源极和漏极区的掺杂剂从掺杂的介电层引入。在一个示例中，栅极结构形成在半导体层的厚度小于10nm的SOI衬底的半导体层上。在与栅极结构相邻的半导体层的至少一部分上形成掺杂介电层。来自掺杂介电层的掺杂剂被驱动到与栅极结构相邻的半导体层的部分中。扩散到半导体中的掺杂剂提供了源极和漏极延伸区域。

67. 发明申请

US20120326230A1 SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE 审中-公开
标题翻译：绝缘子上的绝缘体与低温下形成隔离的补充金属氧化物半导体
公开(公告)号：US20120326230A1
公开(公告)日：2012-12-27
申请号：US13166714
申请日：2011-06-22
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L27/092 , H01L21/762
CPC分类号： H01L29/0649 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) with an isolation formed at a low temperature and methods for constructing the same. An example method includes infusing an insulation material at a low temperature to form a silicon-based insulator between the active regions.
摘要翻译：具有隔离形成在低温下的绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）及其构造方法。一种示例性方法包括在低温下注入绝缘材料以在活性区域之间形成硅基绝缘体。

68. 发明申请

US20120319232A1 Self-Aligned Dual Depth Isolation and Method of Fabrication 失效
标题翻译：自对准双深度隔离和制作方法
公开(公告)号：US20120319232A1
公开(公告)日：2012-12-20
申请号：US13598992
申请日：2012-08-30
申请人： Kangguo Cheng , Robert Heath Dennard , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Robert Heath Dennard , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L29/06
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/76283 , H01L27/1104
摘要： FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.
摘要翻译：提供了FDSOI器件及其制造方法。一方面，一种制造装置的方法包括以下步骤。提供具有基板，BOX和SOI层的晶片。硬掩模层沉积在SOI层上。光致抗蚀剂层沉积在硬掩模层上并且被图案化成一组片段。执行倾斜的植入物以损坏被片段覆盖或遮蔽的硬掩模层的所有部分。移除由植入物损坏的硬掩模层的部分。通过硬掩模层执行第一蚀刻，以在SOI层，BOX和衬底的至少一部分中形成深沟槽。使用图案化的光致抗蚀剂层对硬掩模层进行图案化。通过硬掩模层进行第二蚀刻，以在SOI层中形成浅沟槽。

69. 发明申请

US20120302019A1 NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES 失效
标题翻译： CMOS器件中固体源扩展区非松弛嵌入式压电器
公开(公告)号：US20120302019A1
公开(公告)日：2012-11-29
申请号：US13115314
申请日：2011-05-25
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, JR.
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, JR.
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.
摘要翻译：形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。

70. 发明授权

US08288218B2 Device structure, layout and fabrication method for uniaxially strained transistors 有权
标题翻译：单轴应变晶体管的器件结构，布局和制造方法
公开(公告)号：US08288218B2
公开(公告)日：2012-10-16
申请号：US12689346
申请日：2010-01-19
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译：一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构在活跃地区。在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

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