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61. 发明授权

US08067286B2 Methods of forming recessed access devices associated with semiconductor constructions 有权
标题翻译：形成与半导体结构相关联的凹陷接入设备的方法
公开(公告)号：US08067286B2
公开(公告)日：2011-11-29
申请号：US13012675
申请日：2011-01-24
申请人： Kunal R. Parekh , Suraj J. Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
发明人： Kunal R. Parekh , Suraj J. Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.
摘要翻译：本发明包括形成凹入进入装置的方法。提供基板以在其中具有凹入的接入装置沟槽。一对凹进的接入设备沟槽彼此相邻。导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

62. 发明申请

US20110215436A1 SEMICONDUCTOR DEVICES INCLUDING A DIODE STRUCTURE OVER A CONDUCTIVE STRAP AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES 有权
标题翻译：包括导电条中的二极管结构的半导体器件和形成这样的半导体器件的方法
公开(公告)号：US20110215436A1
公开(公告)日：2011-09-08
申请号：US12715743
申请日：2010-03-02
申请人： Sanh D. Tang , Ming Zhang
发明人： Sanh D. Tang , Ming Zhang
IPC分类号： H01L29/861 , H01L21/762 , H01L21/329
CPC分类号： H01L21/762 , H01L27/2409 , H01L27/2436 , H01L29/861 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed.
摘要翻译：半导体器件包括在导电带上的至少一个二极管。半导体器件可以包括在绝缘体材料上的至少一个导电带，至少一个二极管，包括导电材料上的单晶硅材料，以及至少一个二极管上的存储单元。至少一个二极管可以由单晶硅材料形成。还公开了形成这种半导体器件的方法。

63. 发明授权

US07998813B2 Methods of fabricating an access transistor having a polysilicon-comprising plug on individual of opposing sides of gate material 有权
标题翻译：制造具有多晶硅的插塞的存取晶体管的方法分别位于栅极材料的相对的侧面上
公开(公告)号：US07998813B2
公开(公告)日：2011-08-16
申请号：US12960862
申请日：2010-12-06
申请人： Gordon A. Haller , Sanh D. Tang
发明人： Gordon A. Haller , Sanh D. Tang
IPC分类号： H01L21/336
CPC分类号： H01L21/823437 , H01L21/823412 , H01L27/10823 , H01L27/10826 , H01L27/10844 , H01L29/785
摘要： Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an access device following formation of the periphery transistor gates. Access devices and systems including same are also disclosed.
摘要翻译：集成电路器件中栅极晶体管的制造方法能够形成具有P型工作功能的凹陷接入器件结构或FinFET结构。制造方法还提供了在形成周边晶体管栅极之后形成存取器件的存取晶体管栅极。还公开了包括它们的接入设备和系统。

64. 发明授权

US07939948B2 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads 有权
标题翻译：具有接合焊盘的互连结构和在焊盘上形成凸点位置的方法
公开(公告)号：US07939948B2
公开(公告)日：2011-05-10
申请号：US12409305
申请日：2009-03-23
申请人： Sanh D. Tang , Mark E. Tuttle , Keith R. Cook
发明人： Sanh D. Tang , Mark E. Tuttle , Keith R. Cook
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/04073 , H01L2224/05018 , H01L2224/05026 , H01L2224/05082 , H01L2224/05181 , H01L2224/05187 , H01L2224/05558 , H01L2224/05559 , H01L2224/05571 , H01L2224/05624 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/0496 , H01L2924/05042 , H01L2924/14 , H01L2924/04941 , H01L2224/05552
摘要： Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.
摘要翻译：在焊盘上具有凸起部位的微电子工件以及制造这种凹凸点的方法。例如，这种工件的一个实施例包括具有多个微电子管芯的衬底，该多个微电子管芯包括集成电路和电耦合到集成电路的接合焊盘，例如铜接合焊盘。工件还包括（a）具有多个开口的电介质结构，其中侧壁从相应的接合焊盘突出，以及（b）在相应的接合焊盘上的多个盖。各个盖可以包括附着到接合焊盘和开口的侧壁的阻挡层的分立部分，以及阻挡层上的覆盖层的离散部分。盖子彼此电隔离并且与相应的接合焊盘自对准，而不在盖层上形成掩模层。

65. 发明授权

US07929343B2 Methods, devices, and systems relating to memory cells having a floating body 有权
标题翻译：与具有浮体的存储单元有关的方法，装置和系统
公开(公告)号：US07929343B2
公开(公告)日：2011-04-19
申请号：US12419658
申请日：2009-04-07
申请人： Sanh D. Tang
发明人： Sanh D. Tang
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , H01L27/108 , H01L27/10802
摘要： Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may further include a bias gate recessed into the silicon and positioned between an isolation region and the transistor. In addition, the bias gate may be configured to be operably coupled to a bias voltage. The memory cell may also include a floating body within the silicon. The floating body may include a first portion adjacent the source and the drain and vertically offset from the bias gate and a second portion coupled to the first portion. Moreover, the bias gate may be formed adjacent to the second portion.
摘要翻译：公开了涉及具有浮体的存储单元的方法，装置和系统。存储单元包括晶体管，其包括各自形成在硅中的漏极和源极以及位于漏极和源极之间的栅极。存储单元还可以包括凹入硅中并且位于隔离区域和晶体管之间的偏置栅极。此外，偏置栅极可以被配置为可操作地耦合到偏置电压。存储单元还可以包括硅内的浮体。浮体可以包括邻近源极和漏极的第一部分，并且垂直偏离偏置栅极，第二部分耦合到第一部分。此外，偏置栅极可以形成为与第二部分相邻。

66. 发明申请

US20110081755A1 Methods Of Fabricating An Access Transistor Having A Polysilicon-Comprising Plug On Individual Of Opposing Sides Of Gate Material 有权
标题翻译：制造接触晶体管的方法，该晶体管在栅极材料的相对侧上具有多晶硅组成的插塞
公开(公告)号：US20110081755A1
公开(公告)日：2011-04-07
申请号：US12960862
申请日：2010-12-06
申请人： Gordon A. Haller , Sanh D. Tang
发明人： Gordon A. Haller , Sanh D. Tang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , H01L21/823412 , H01L27/10823 , H01L27/10826 , H01L27/10844 , H01L29/785
摘要： Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an access device following formation of the periphery transistor gates. Access devices and systems including same are also disclosed.
摘要翻译：集成电路器件中栅极晶体管的制造方法能够形成具有P型工作功能的凹陷接入器件结构或FinFET结构。制造方法还提供了在形成周边晶体管栅极之后形成存取器件的存取晶体管栅极。还公开了包括它们的接入设备和系统。

67. 发明授权

US07589995B2 One-transistor memory cell with bias gate 有权
标题翻译：具有偏置栅极的单晶体管存储单元
公开(公告)号：US07589995B2
公开(公告)日：2009-09-15
申请号：US11516814
申请日：2006-09-07
申请人： Sanh D. Tang , Gordon Haller , Daniel H. Doyle
发明人： Sanh D. Tang , Gordon Haller , Daniel H. Doyle
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C11/401 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10844
摘要： One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.
摘要翻译：单晶体管（1T）无电容器DRAM单元各自包括具有将浮体区域与基底基板分离的偏置栅极层的MOS晶体管。 MOS晶体管用作存储器件，不需要存储电容器。通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子他们在哪里举行。

68. 发明申请

US20090207649A1 VERTICAL WRAP-AROUND-GATE FIELD-EFFECT-TRANSISTOR FOR HIGH DENSITY, LOW VOLTAGE LOGIC AND MEMORY ARRAY 有权
标题翻译：用于高密度，低电压逻辑和存储器阵列的垂直封装栅极场效应晶体管
公开(公告)号：US20090207649A1
公开(公告)日：2009-08-20
申请号：US12417128
申请日：2009-04-02
申请人： Sanh D. Tang , Robert J. Burke , Anand Srinivasan
发明人： Sanh D. Tang , Robert J. Burke , Anand Srinivasan
IPC分类号： G11C11/24 , H01L29/92 , H01L27/10 , G11C8/00 , G11C7/00 , H01L29/786
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10876 , H01L27/10891 , H01L27/1203 , H01L29/42392 , H01L29/78642
摘要： A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
摘要翻译：具有环绕栅极的垂直晶体管和制造这种晶体管的方法。环绕栅极（WAG）垂直晶体管通过其中晶体管的源极，漏极和沟道区域通过制造工艺自动限定和对准而不进行光刻图案化的工艺制造。

69. 发明授权

US07528439B2 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array 有权
标题翻译：用于高密度，低电压逻辑和存储器阵列的垂直环绕栅极场效应晶体管
公开(公告)号：US07528439B2
公开(公告)日：2009-05-05
申请号：US11438419
申请日：2006-05-23
申请人： Sanh D. Tang , Robert J. Burke , Anand Srinivasan
发明人： Sanh D. Tang , Robert J. Burke , Anand Srinivasan
IPC分类号： H01L29/732
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10876 , H01L27/10891 , H01L27/1203 , H01L29/42392 , H01L29/78642
摘要： A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
摘要翻译：具有环绕栅极的垂直晶体管和制造这种晶体管的方法。环绕栅极（WAG）垂直晶体管通过其中晶体管的源极，漏极和沟道区域通过制造工艺自动限定和对准而不进行光刻图案化的工艺制造。

70. 发明授权

US07528064B2 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads 有权
标题翻译：具有接合焊盘的互连结构和在焊盘上形成凸点位置的方法
公开(公告)号：US07528064B2
公开(公告)日：2009-05-05
申请号：US11872607
申请日：2007-10-15
申请人： Sanh D. Tang , Mark E. Tuttle , Keith R. Cook
发明人： Sanh D. Tang , Mark E. Tuttle , Keith R. Cook
IPC分类号： H01L21/4763
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/04073 , H01L2224/05018 , H01L2224/05026 , H01L2224/05082 , H01L2224/05181 , H01L2224/05187 , H01L2224/05558 , H01L2224/05559 , H01L2224/05571 , H01L2224/05624 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/0496 , H01L2924/05042 , H01L2924/14 , H01L2924/04941 , H01L2224/05552
摘要： Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.
摘要翻译：在焊盘上具有凸起部位的微电子工件以及制造这种凹凸点的方法。例如，这种工件的一个实施例包括具有多个微电子管芯的衬底，该多个微电子管芯包括集成电路和电耦合到集成电路的接合焊盘，例如铜接合焊盘。工件还包括（a）具有多个开口的电介质结构，其中侧壁从相应的接合焊盘突出，以及（b）在相应的接合焊盘上的多个盖。各个盖可以包括附着到接合焊盘和开口的侧壁的阻挡层的分立部分，以及阻挡层上的覆盖层的离散部分。盖子彼此电隔离并且与相应的接合焊盘自对准，而不在盖层上形成掩模层。

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