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61. 发明申请

US20110027948A1 METHOD FOR MANUFACTURING A FINFET DEVICE 有权
标题翻译：制造FINFET器件的方法
公开(公告)号：US20110027948A1
公开(公告)日：2011-02-03
申请号：US12533389
申请日：2009-07-31
申请人： Zhibin Ren , Xinhui Wang , Kevin K. Chan , Ying Zhang
发明人： Zhibin Ren , Xinhui Wang , Kevin K. Chan , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method for manufacturing a FinFET device includes: providing a substrate having a mask disposed thereon; covering portions of the mask to define a perimeter of a gate region; removing uncovered portions of the mask to expose the substrate; covering a part of the exposed substrate with another mask to define at least one fin region; forming the at least one fin and the gate region through both masks and the substrate, the gate region having side walls; disposing insulating layers around the at least one fin and onto the side walls; disposing a conductive material into the gate region and onto the insulating layers to form a gate electrode, and then forming source and drain regions.
摘要翻译：一种制造FinFET器件的方法包括：提供其上设置有掩模的衬底; 覆盖掩模的部分以限定栅极区域的周边; 去除所述掩模的未覆盖部分以暴露所述基底; 用另一掩模覆盖暴露的基底的一部分以限定至少一个鳍片区域; 通过所述掩模和所述基板形成所述至少一个翅片和所述栅极区域，所述栅极区域具有侧壁; 将所述至少一个翅片周围的绝缘层设置在所述侧壁上; 将导电材料设置在栅极区域和绝缘层上以形成栅电极，然后形成源极和漏极区域。

62. 发明授权

US07494886B2 Uniaxial strain relaxation of biaxial-strained thin films using ion implantation 失效
标题翻译：使用离子注入的双轴应变薄膜的单轴应变弛豫
公开(公告)号：US07494886B2
公开(公告)日：2009-02-24
申请号：US11622524
申请日：2007-01-12
申请人： Zhibin Ren , Katherine L. Saenger , Haizhou Yin
发明人： Zhibin Ren , Katherine L. Saenger , Haizhou Yin
IPC分类号： H01L21/336 , H01L21/04 , H01L21/425
CPC分类号： H01L21/26506 , H01L21/823807 , H01L29/78 , H01L29/7848 , Y10S438/938
摘要： A method for achieving uniaxial strain on originally biaxial-strained thin films after uniaxial strain relaxation induced by ion implantation is provided. The biaxial-strained thin film receives ion implantation after being covered by a patterned implant block structure. The strain in the uncovered region is relaxed by ion implantation, which induces the lateral strain relaxation in the covered region. When the implant block structure is narrow (dimension is comparable to the film thickness), the original biaxial strain will relax uniaxially in the lateral direction.
摘要翻译：提供了一种通过离子注入诱发的单轴应变松弛之后实现原始双轴应变薄膜单轴应变的方法。双轴应变薄膜在被图案化的植入物块结构覆盖之后接收离子注入。未覆盖区域的应变通过离子注入而松弛，这引起覆盖区域的横向应变弛豫。当植入物块结构窄（尺寸与膜厚度相当）时，原始双轴应变将在横向方向上单轴弛豫。

63. 发明申请

US20090045462A1 ULTRATHIN SOI CMOS DEVICES EMPLOYING DIFFERENTIAL STI LINERS 失效
标题翻译： ULTRATHIN SOI CMOS器件采用差分STI衬线
公开(公告)号：US20090045462A1
公开(公告)日：2009-02-19
申请号：US11839272
申请日：2007-08-15
申请人： Zhibin Ren , Ghavam Shahidi , Dinkar V. Singh , Jeffrey W. Sleight , Xinhui Wang
发明人： Zhibin Ren , Ghavam Shahidi , Dinkar V. Singh , Jeffrey W. Sleight , Xinhui Wang
IPC分类号： H01L21/8238 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76229 , H01L21/76283 , H01L27/1203 , H01L29/7846
摘要： An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
摘要翻译：在包含硅的顶部半导体层的超薄绝缘体上的基板上形成氧氮化物衬垫层和掩模层。浅沟槽的第一部分通过NFET区域和蚀刻的光刻掩模在顶部半导体层中图案化，其中埋入绝缘体层的暴露部分凹陷并且顶部半导体层被切割。在PFET有源区的暴露的侧壁和底部周边表面上形成厚的热氧化硅衬垫以施加高横向压应力。浅沟槽的第二部分通过包括PFET有源区的PFET区域的光刻掩模形成。在NFET有源区的暴露的侧壁上形成薄的热氧化硅或不存在热氧化硅，其经受低的侧向压应力或没有横向压应力。

64. 发明授权

US07002214B1 Ultra-thin body super-steep retrograde well (SSRW) FET devices 有权
标题翻译：超薄体超陡逆行井（SSRW）FET器件
公开(公告)号：US07002214B1
公开(公告)日：2006-02-21
申请号：US10710736
申请日：2004-07-30
申请人： Diane C. Boyd , Judson R. Holt , MeiKei Ieong , Renee T. Mo , Zhibin Ren , Ghavam G. Shahidi
发明人： Diane C. Boyd , Judson R. Holt , MeiKei Ieong , Renee T. Mo , Zhibin Ren , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/823892 , H01L21/84 , H01L29/66772 , H01L29/78609 , H01L29/78618 , H01L29/78696
摘要： A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.
摘要翻译：超陡逆行井场效应晶体管器件的制造方法从形成在衬底上的SOI层开始。掩埋氧化层。使SOI层变薄以形成超薄SOI层。形成将SOI层分离成N和P接地平面区域的隔离沟槽。用高水平的N型和P型掺杂剂掺杂由SOI层形成的N和P接地平面区域。在N和P接地平面区域之上形成半导体沟道区。在沟道区域上方形成FET源极和漏极区域以及栅极电极堆叠。可选地，在SOI接地平面区域和沟道区域之间形成扩散延迟层。

65. 发明授权

US08637381B2 High-k dielectric and silicon nitride box region 失效
标题翻译：高k电介质和氮化硅盒区域
公开(公告)号：US08637381B2
公开(公告)日：2014-01-28
申请号：US13274381
申请日：2011-10-17
申请人： Effendi Leobandung , Dae-Gyu Park , Shom S. Ponoth , Zhibin Ren , Ghavam G. Shahidi , Leathen Shi
发明人： Effendi Leobandung , Dae-Gyu Park , Shom S. Ponoth , Zhibin Ren , Ghavam G. Shahidi , Leathen Shi
IPC分类号： H01L27/092 , H01L21/336 , H01L27/12 , H01L21/762 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/76251 , H01L29/78603
摘要： Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.
摘要翻译：本发明的各方面提供了在晶片蚀刻处理期间防止底切并且增强了后栅极到沟道电耦合。在一个实施例中，本发明的方面包括半导体结构，包括：高体积硅晶片顶部的高k掩埋氧化物（BOX）层，高k BOX层包括：至少一个氮化硅层; 和高k电介质层; 以及位于高k BOX层顶上的绝缘体上硅（SOI）层。

66. 发明授权

US08288826B2 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) 有权
标题翻译：绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）
公开(公告)号：US08288826B2
公开(公告)日：2012-10-16
申请号：US13290634
申请日：2011-11-07
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L29/76 , H01L21/00
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
摘要翻译：绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

67. 发明申请

US20120168864A1 SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE 审中-公开
标题翻译：用于改善短路通道效应控制，对准电容和接头泄漏的自对准井
公开(公告)号：US20120168864A1
公开(公告)日：2012-07-05
申请号：US13418862
申请日：2012-03-13
申请人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
发明人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
IPC分类号： H01L29/772
CPC分类号： H01L29/66772 , H01L21/26586 , H01L21/823814 , H01L29/105 , H01L29/66492 , H01L29/66537 , H01L29/66545 , H01L29/66659 , H01L29/7848 , H01L29/78654 , H01L29/78696
摘要： A transistor device includes a patterned gate structure formed over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers; and a doped well implant formed in the substrate, the well implant being self-aligned with the patterned gate structure.
摘要翻译：晶体管器件包括形成在衬底上的图案化栅极结构，所述图案化栅极结构包括栅极导体，栅极电介质层和侧壁间隔物; 以及形成在衬底中的掺杂阱注入，阱注入与图案化栅极结构自对准。

68. 发明授权

US08053373B2 Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX) 有权
标题翻译：绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）
公开(公告)号：US08053373B2
公开(公告)日：2011-11-08
申请号：US12123706
申请日：2008-05-20
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L21/31 , H01L29/76
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
摘要翻译：绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

69. 发明授权

US08043920B2 finFETS and methods of making same 有权
标题翻译： finFETs及其制作方法
公开(公告)号：US08043920B2
公开(公告)日：2011-10-25
申请号：US12561606
申请日：2009-09-17
申请人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
发明人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
IPC分类号： H01L21/00
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.
摘要翻译：一种合并多鳍鳍鳍鳍片的制造方法和结构。该方法包括从具有非常薄的掩埋氧化物层的SOI衬底的硅层形成单晶硅散热片，并通过从衬底生长垂直外延硅并从散热片的端部生成水平外延硅，从而将翅片的端部区域合并垂直外延硅生长占优势。

70. 发明授权

US07989297B2 Asymmetric epitaxy and application thereof 有权
标题翻译：不对称外延及其应用
公开(公告)号：US07989297B2
公开(公告)日：2011-08-02
申请号：US12614699
申请日：2009-11-09
申请人： Haizhou Yin , Xinhui Wang , Kevin K. Chan , Zhibin Ren
发明人： Haizhou Yin , Xinhui Wang , Kevin K. Chan , Zhibin Ren
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。所述方法包括在半导体衬底的顶部上形成栅极结构，所述栅极结构包括栅极叠层和邻近所述栅极堆叠的侧壁的间隔物，并且具有与所述第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。还提供了由此形成的半导体结构。

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