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61. 发明申请

US20110101440A1 TWO PFET SOI MEMORY CELLS 审中-公开
标题翻译：两个PFET SOI存储器单元
公开(公告)号：US20110101440A1
公开(公告)日：2011-05-05
申请号：US12612710
申请日：2009-11-05
申请人： Jin Cai , Brian L. Ji , Tak Hung Ning
发明人： Jin Cai , Brian L. Ji , Tak Hung Ning
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823425 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L27/11521 , H01L27/11558 , H01L29/792
摘要： A CMOS device includes a silicon substrate and an electrical insulator formed over the silicon substrate. The device also includes an access pFET formed over the electrical insulator and a first gate stack and a storage pFET formed over the electrical insulator, the storage pFET including a second source region that is co-formed with the first drain region, a second channel region, and a second drain region. The device also includes a second gate stack including a second dielectric layer formed above the second channel region and a floating gate electrode formed above the second gate dielectric layer.
摘要翻译： CMOS器件包括硅衬底和形成在硅衬底上的电绝缘体。器件还包括形成在电绝缘体上的访问pFET和形成在电绝缘体上的第一栅极堆叠和存储pFET，存储pFET包括与第一漏极区域共同形成的第二源极区域，第二沟道区域，和第二漏区。该器件还包括第二栅极堆叠，其包括形成在第二沟道区上方的第二介电层和形成在第二栅极介电层上方的浮置栅电极。

62. 发明授权

US07867866B2 SOI FET with source-side body doping 有权
标题翻译：具有源极体掺杂的SOI FET
公开(公告)号：US07867866B2
公开(公告)日：2011-01-11
申请号：US12651499
申请日：2010-01-04
申请人： Jin Cai , Tak Hung Ning
发明人： Jin Cai , Tak Hung Ning
IPC分类号： H01L21/336 , H01L31/119
CPC分类号： H01L29/78612 , H01L29/66772
摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.
摘要翻译：提出了一种具有改进的浮体的SOI FET器件。体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

63. 发明申请

US20100039852A1 Dynamic Memory Cell Methods 有权
标题翻译：动态记忆单元方法
公开(公告)号：US20100039852A1
公开(公告)日：2010-02-18
申请号：US12542802
申请日：2009-08-18
申请人： Wing K. Luk , Jin Cai
发明人： Wing K. Luk , Jin Cai
IPC分类号： G11C11/24 , H01L21/8242 , G11C7/00
CPC分类号： G11C11/4097 , G11C7/18 , G11C8/16 , G11C11/405 , H01L21/28079 , H01L21/84 , H01L27/10873 , H01L29/495
摘要： A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.
摘要翻译：公开了一种动态随机存取存储器单元，其包括电容存储器件和写入存取晶体管。写入存取晶体管可操作地耦合到电容存储器件，并且具有包括高K电介质的栅极堆叠，其中高K电介质具有大于二氧化硅介电常数的介电常数。还公开了使用这些单元的存储器阵列，使用存储器阵列的计算装置，存储数据的方法和制造方法。

64. 发明申请

US20090321831A1 PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION 有权
标题翻译：具有金属化源侧HALO区域的部分沉积SOI场效应晶体管
公开(公告)号：US20090321831A1
公开(公告)日：2009-12-31
申请号：US12554344
申请日：2009-09-04
申请人： Jin Cai , Wilfried Haensch , Amlan Majumdar
发明人： Jin Cai , Wilfried Haensch , Amlan Majumdar
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/458 , H01L29/66772 , H01L29/78612 , H01L29/78624
摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.
摘要翻译：源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

65. 发明授权

US08901680B2 Graphene pressure sensors 有权
标题翻译：石墨烯压力传感器
公开(公告)号：US08901680B2
公开(公告)日：2014-12-02
申请号：US13445029
申请日：2012-04-12
申请人： Jin Cai , Yanqing Wu , Wenjuan Zhu
发明人： Jin Cai , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L29/06
CPC分类号： H01L29/1606 , G01L9/0042 , G01L9/0051 , H01L27/0802 , H01L29/0649
摘要： Semiconductor nano pressure sensor devices having graphene membrane suspended over cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.
摘要翻译：半导体纳米压力传感器装置具有悬浮在形成于半导体衬底中的空腔上的石墨烯膜。悬浮的石墨烯膜用作用于感测压力（其可以制成非常薄）从约一个原子层到约10个原子层的活性电子机械膜，以提高半导体压力传感器装置的灵敏度和可靠性。

66. 发明授权

US08604532B2 Computing apparatus employing dynamic memory cell structures 有权
标题翻译：采用动态存储单元结构的计算设备
公开(公告)号：US08604532B2
公开(公告)日：2013-12-10
申请号：US12542801
申请日：2009-08-18
申请人： Win K. Luk , Jin Cai
发明人： Win K. Luk , Jin Cai
IPC分类号： H01L27/108
CPC分类号： G11C11/4097 , G11C7/18 , G11C8/16 , G11C11/405 , H01L21/28079 , H01L21/84 , H01L27/10873 , H01L29/495
摘要： A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.
摘要翻译：公开了一种动态随机存取存储器单元，其包括电容存储器件和写入存取晶体管。写入存取晶体管可操作地耦合到电容存储器件，并且具有包括高K电介质的栅极堆叠，其中高K电介质具有大于二氧化硅介电常数的介电常数。还公开了使用这些单元的存储器阵列，使用存储器阵列的计算装置，存储数据的方法和制造方法。

67. 发明授权

US08603876B2 Dynamic memory cell methods 有权
标题翻译：动态存储单元方法
公开(公告)号：US08603876B2
公开(公告)日：2013-12-10
申请号：US12542802
申请日：2009-08-18
申请人： Win K. Luk , Jin Cai
发明人： Win K. Luk , Jin Cai
IPC分类号： H01L21/8242
CPC分类号： G11C11/4097 , G11C7/18 , G11C8/16 , G11C11/405 , H01L21/28079 , H01L21/84 , H01L27/10873 , H01L29/495
摘要： A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.
摘要翻译：公开了一种动态随机存取存储器单元，其包括电容存储器件和写入存取晶体管。写入存取晶体管可操作地耦合到电容存储器件，并且具有包括高K电介质的栅极堆叠，其中高K电介质具有大于二氧化硅介电常数的介电常数。还公开了使用这些单元的存储器阵列，使用存储器阵列的计算装置，存储数据的方法和制造方法。

68. 发明申请

US20130175661A1 Integrated Circuit Having Back Gating, Improved Isolation And Reduced Well Resistance And Method To Fabricate Same 审中-公开
标题翻译：集成电路具有后门控，改进隔离和降低电阻以及制造方法
公开(公告)号：US20130175661A1
公开(公告)日：2013-07-11
申请号：US13623198
申请日：2012-09-20
申请人： Jin Cai , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Jin Cai , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/76232 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A structure includes a silicon substrate; at least two wells in the silicon substrate; and a deep trench isolation (DTI) separating the two wells. The DTI has a top portion and a bottom portion having a width that is larger than a width of the top portion. The structure further includes at least two semiconductor devices disposed over one of the wells, where the at least two semiconductor devices are separated by a shallow trench isolation (STI). In the structure sidewalls of the top portion of the DTI and sidewalls of the STI are comprised of doped, re-crystallized silicon. The doped, re-crystallized silicon can be formed by an angled ion implant that uses, for example, one of Xe, In, BF2, B18H22, C16H10, Si, Ge or As as an implant species to amorphize the silicon, and by annealing the amorphized silicon to re-crystallize the amorphized silicon.
摘要翻译：一种结构包括硅衬底; 硅衬底中的至少两个孔; 和分离两口井的深沟槽隔离（DTI）。 DTI具有顶部和底部，其宽度大于顶部的宽度。该结构还包括设置在一个阱中的至少两个半导体器件，其中至少两个半导体器件由浅沟槽隔离（STI）隔开。在DTI的顶部部分和STI的侧壁的结构中，由掺杂的再结晶硅组成。掺杂的再结晶硅可以通过使用例如Xe，In，BF 2，B 18 H 22，C 16 H 10，Si，Ge或As中的一种的成角度的离子注入来形成，以使硅非晶化，并且通过退火非晶化硅使非晶化硅再结晶。

69. 发明授权

US08415743B2 ETSOI CMOS with back gates 有权
标题翻译：带后门的ETSOI CMOS
公开(公告)号：US08415743B2
公开(公告)日：2013-04-09
申请号：US13114410
申请日：2011-05-24
申请人： Jin Cai , Robert H Dennard , Ali Khakifirooz
发明人： Jin Cai , Robert H Dennard , Ali Khakifirooz
IPC分类号： H01L27/092
CPC分类号： H01L27/1203
摘要： A structure has a functional region having a first type of conductivity and a top surface. The functional region is connected to a bias contact. The structure further includes an insulating layer; a semiconductor layer and first and second transistor devices having the same type of conductivity disposed upon the semiconductor layer. The structure further includes a first back gate region adjacent to the top surface and underlying one of the transistor devices, the first back gate region having a second type of conductivity; and a second back gate region adjacent to the top surface and underlying the other one of the transistor devices, the second back gate region having the first type of conductivity. The first transistor device has a first characteristic threshold voltage and the second transistor device has a second characteristic threshold voltage that differs from the first characteristic threshold voltage.
摘要翻译：结构具有具有第一类型的导电性的功能区域和顶表面。功能区域连接到偏置触点。该结构还包括绝缘层; 半导体层和具有相同类型导电性的第一和第二晶体管器件设置在半导体层上。所述结构还包括与所述顶表面相邻并且位于所述晶体管器件之一下方的第一后栅极区域，所述第一背栅极区域具有第二类型的导电性; 以及与顶表面相邻并且位于另一个晶体管器件下方的第二背栅极区域，第二背栅极区域具有第一类型的导电性。第一晶体管器件具有第一特征阈值电压，并且第二晶体管器件具有不同于第一特征阈值电压的第二特征阈值电压。

70. 发明授权

US08349684B2 Semiconductor device with high K dielectric control terminal spacer structure 有权
标题翻译：具有高K介质控制端子间隔结构的半导体器件
公开(公告)号：US08349684B2
公开(公告)日：2013-01-08
申请号：US12622115
申请日：2009-11-19
申请人： Jin Cai , Amlan Majumdar , Ramachandran Muralidhar , Ghavam G. Shahidi
发明人： Jin Cai , Amlan Majumdar , Ramachandran Muralidhar , Ghavam G. Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region.
摘要翻译：一种半导体器件，包括由高K电介质材料制成的控制端子侧壁间隔结构。半导体器件包括控制端子，其中间隔结构是用于控制端子的侧壁间隔结构。半导体器件包括位于衬底中的电流端子区域。在一些示例中，间隔结构的高度小于控制端的高度。在一些示例中，间隔结构包括位于第一电流端子区域和第二电流端子区域之间的衬底的区域上方的部分。

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