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61. 发明申请

US20120132998A1 Replacement Metal Gate Structures Providing Independent Control On Work Function and Gate Leakage Current 失效
标题翻译：替代金属栅极结构提供工作功能和栅极泄漏电流的独立控制
公开(公告)号：US20120132998A1
公开(公告)日：2012-05-31
申请号：US12954946
申请日：2010-11-29
申请人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
发明人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/49 , H01L29/513 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.
摘要翻译：可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类型场效应晶体管的区域中的势垒金属层上。导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

62. 发明申请

US20120061798A1 HIGH CAPACITANCE TRENCH CAPACITOR 有权
标题翻译：高电容式电容器
公开(公告)号：US20120061798A1
公开(公告)日：2012-03-15
申请号：US12881481
申请日：2010-09-14
申请人： Keich Kwong Hon Wong , Ramachandra Divakaruni , Roger A. Booth, JR.
发明人： Keich Kwong Hon Wong , Ramachandra Divakaruni , Roger A. Booth, JR.
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.
摘要翻译：双节点介质沟槽电容器包括在沟槽中形成的一叠层。层的堆叠包括从底部到顶部的第一导电层，第一节点电介质层，第二导电层，第二节点电介质层和第三导电层。双节点介电沟槽电容器包括两个背对背电容器，其包括第一电容器和第二电容器。第一电容器包括第一导电层，第一节点电介质层，第二导电层，第二电容器包括第二导电层，第二节点电介质层和第三导电层。双节点介质沟槽电容器可以提供使用具有与第一和第二节点电介质层相当的组成和厚度的单节点电介质层的沟槽电容器的大约两倍的电容。

63. 发明申请

US20110169065A1 METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES 有权
标题翻译：在半导体绝缘体（SOI）衬底上形成电容器和存储器件的方法和结构
公开(公告)号：US20110169065A1
公开(公告)日：2011-07-14
申请号：US12686403
申请日：2010-01-13
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L27/06 , H01L21/8242
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1087 , H01L27/10894 , H01L27/1203 , H01L29/66181
摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.
摘要翻译：提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。还提供了一种用于形成上述装置的方法。

64. 发明授权

US07935998B2 Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same 有权
标题翻译：绝缘体上半导体沟槽器件的自对准体接触及其制造方法
公开(公告)号：US07935998B2
公开(公告)日：2011-05-03
申请号：US12053692
申请日：2008-03-24
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L23/02
CPC分类号： H01L29/7827 , H01L21/84 , H01L27/0207 , H01L27/10841 , H01L27/10876 , H01L29/66666 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of forming a body contact for a semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.
摘要翻译：形成绝缘体上半导体沟槽器件的体接触的结构和方法。该方法包括：在基板的顶表面上形成一组心轴，该组心轴的每个心轴布置在多边形的不同角上并且在衬底的顶表面上方延伸，该心轴组中的多个心轴等于多边形的多个角; 在所述一组心轴的每个心轴的侧壁上形成侧壁间隔件，每个相邻的一对心轴的侧壁间隔件彼此合并并且形成在多边形的内部区域中限定开口的不间断的壁，开口蚀刻开口中的衬底中的接触沟槽; 以及用导电材料填充接触沟槽以形成接触。

65. 发明授权

US07776706B2 Forming SOI trench memory with single-sided buried strap 失效
标题翻译：形成具有单面埋地带的SOI沟槽存储器
公开(公告)号：US07776706B2
公开(公告)日：2010-08-17
申请号：US12169727
申请日：2008-07-09
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/8234
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

66. 发明授权

US07759188B2 Method of fabricating vertical body-contacted SOI transistor 失效
标题翻译：垂直体接触SOI晶体管的制造方法
公开(公告)号：US07759188B2
公开(公告)日：2010-07-20
申请号：US12002828
申请日：2007-12-19
申请人： Kangguo Cheng , Gary B. Bronner , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Gary B. Bronner , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译：提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域的沟渠衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

67. 发明授权

US07737502B2 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain 有权
标题翻译：用于提高源/漏极的应变Si / SGOI结构上的多栅极氧化和侧壁保护的提高的STI工艺
公开(公告)号：US07737502B2
公开(公告)日：2010-06-15
申请号：US11351801
申请日：2006-02-10
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
IPC分类号： H01L27/088
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

68. 发明授权

US07737482B2 Self-aligned strap for embedded trench memory on hybrid orientation substrate 失效
标题翻译：用于混合取向基板上嵌入式沟槽存储器的自对准带
公开(公告)号：US07737482B2
公开(公告)日：2010-06-15
申请号：US11538982
申请日：2006-10-05
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L27/1207 , H01L29/78
摘要： Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in the bulk semiconductor section; and a self-aligned strap extending from a source/drain region of the transistor to an electrode of the trench capacitor. The method does not require additional masks to generate the strap, results in a self-aligned strap and improved device performance. In one embodiment, the strap is a silicide strap.
摘要翻译：公开了包括用于混合取向技术（HOT）衬底上的嵌入式沟槽存储器（例如，沟槽电容器）的自对准带的结构以及相关方法。一种结构包括：包含绝缘体上半导体（SOI）部分和体半导体部分的混合取向衬底; SOI部分上的晶体管; 体半导体部分中的沟槽电容器; 以及从晶体管的源极/漏极区域延伸到沟槽电容器的电极的自对准带。该方法不需要额外的掩模来生成带，导致自对准带和改进的设备性能。在一个实施例中，带是硅化物带。

69. 发明授权

US07700434B2 Trench widening without merging 失效
标题翻译：沟槽加宽而不合并
公开(公告)号：US07700434B2
公开(公告)日：2010-04-20
申请号：US11957615
申请日：2007-12-17
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L29/66181
摘要： A semiconductor fabrication method. First, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench includes a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. Next, portions of the blocking layer on the {110} side wall surfaces are removed without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
摘要翻译：半导体制造方法。首先，提供半导体结构。半导体结构包括半导体衬底，半导体衬底中的沟槽。沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。接下来，除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围环境。

70. 发明授权

US07601646B2 Top-oxide-early process and array top oxide planarization 有权
标题翻译：顶部氧化物早期过程和阵列顶部氧化物平面化
公开(公告)号：US07601646B2
公开(公告)日：2009-10-13
申请号：US10710566
申请日：2004-07-21
申请人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
发明人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/311
CPC分类号： H01L27/10894 , H01L21/31053 , H01L27/10841 , H01L27/10897
摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
摘要翻译：通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部氧化物晚期过程。新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

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