专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US06211071B1 Optimized trench/via profile for damascene filling 有权
标题翻译：用于镶嵌填料的优化沟槽/通孔型材
公开(公告)号：US06211071B1
公开(公告)日：2001-04-03
申请号：US09296552
申请日：1999-04-22
申请人： Todd P. Lukanc , Fei Wang , Steven C. Avanzino
发明人： Todd P. Lukanc , Fei Wang , Steven C. Avanzino
IPC分类号： H01L214763
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/31133 , H01L21/76804 , H01L21/76829 , H01L21/76831 , H01L21/76843 , H01L21/76877
摘要： In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improve reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing “pinching-off” of the recess opening due to overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Further embodiments include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer. The tapered width profile of the recess effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during electroplating for filling the recesses.
摘要翻译：在电介质层的表面形成例如铜或铜合金的成网金属化图案，通过电镀无孔地填充形成在电介质层表面的凹槽，从而显着提高可靠性。实施例包括由于局部增加的沉积速率而导致由于在开口的角部处的悬垂成核/种子层沉积而导致的凹陷开口的“夹断”。另外的实施例包括提供包括不同介电材料的双层电介质层，并执行电介质层的上层的第一，各向同性蚀刻工艺，用于选择性地使凹口开口的宽度变窄，以在衬底表面提供更宽的开口，随后进行第二种各向异性蚀刻工艺，用于将凹槽以基本上恒定的宽度延伸到介电层的下层中的预定深度。凹陷的锥形宽度轮廓有效地防止了在其中形成悬垂沉积物，这可能导致电镀期间的闭塞和空隙形成以填充凹部。

62. 发明授权

US06184141B2 Method for multiple phase polishing of a conductive layer in a semidonductor wafer 有权
标题翻译：半导体晶片中导电层的多相抛光方法
公开(公告)号：US06184141B2
公开(公告)日：2001-02-06
申请号：US09198369
申请日：1998-11-24
申请人： Steven C. Avanzino , Kashmir S. Sahota , Gerd Marxsen
发明人： Steven C. Avanzino , Kashmir S. Sahota , Gerd Marxsen
IPC分类号： H01L2100
CPC分类号： H01L21/3212
摘要： A method of planarizing a copper containing conductive layer of a semiconductor wafer forms a blanketing copper containing layer within and upon a patterned substrate layer. Chemical mechanical polish (CMP) planarizing is performed on the copper containing layer at a relatively fast rate of removal until most of the layer is removed. The remaining portion of the layer is then CMP planarized at a second rate of removal, which is slower than the first rate of removal, until the copper containing layer is substantially completely removed and a barrier layer underlying the copper containing layer is reached. The multiple phase planarization of the copper containing layer avoids excessive dishing and pattern erosion while maintaining high throughput and uniform removal.
摘要翻译：平面化半导体晶片的含铜导电层的方法在图案化的衬底层的内部和之上形成覆盖铜的层。化学机械抛光（CMP）平面化在含铜层上以相对较快的去除速率进行，直到大部分层被去除。然后将层的剩余部分以第二除去速率平坦化，其比第一脱除速率慢，直到基本上完全除去含铜层，并且到达含铜层下面的阻挡层。含铜层的多相平面化避免了过度的凹陷和图案侵蚀，同时保持了高产量和均匀的去除。

63. 发明授权

US6117782A Optimized trench/via profile for damascene filling 有权
标题翻译：用于镶嵌填料的优化沟槽/通孔型材
公开(公告)号：US6117782A
公开(公告)日：2000-09-12
申请号：US296556
申请日：1999-04-22
申请人： Todd P. Lukanc , Fei Wang , Steven C. Avanzino
发明人： Todd P. Lukanc , Fei Wang , Steven C. Avanzino
IPC分类号： H01L21/768 , H01L21/00
CPC分类号： H01L21/76873 , H01L21/76804 , H01L21/7684 , H01L21/76843 , H01L21/7688
摘要： In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improved reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing "pinching-off" of the recess opening due overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Embodiments also include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper (sacrificial) lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer. The tapered width profile of the recess effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during electroplating for filling the recesses. After electroplating, the recess-filled, plated surface is subjected to planarization processing, as by CMP, wherein the entire thickness of the second, upper lamina of the dielectric layer is removed.
摘要翻译：在电介质层的表面上形成例如铜或铜合金的嵌入式金属化图案，通过电镀无孔地填充在电介质层表面中形成的凹槽，从而显着提高了可靠性。实施例包括由于局部增加的沉积速率，在开口的角部处由于突出的成核/种子层沉积而阻止凹口的“夹断”。实施例还包括提供包括不同电介质材料的双层电介质层，并且执行电介质层的上（牺牲）层的第一，各向同性蚀刻工艺，用于选择性地使凹口开口的宽度变窄，从而在衬底表面，随后进行第二种各向异性蚀刻工艺，用于以基本上恒定的宽度将凹槽延伸到介电层的下层中的预定深度。凹陷的锥形宽度轮廓有效地防止了在其中形成悬垂沉积物，这可能导致电镀期间的闭塞和空隙形成以填充凹部。在电镀之后，通过CMP对凹陷填充的镀覆表面进行平坦化处理，其中去除介电层的第二上层的整个厚度。

64. 发明授权

US5916855A Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films 失效
标题翻译：化学机械抛光浆料配方及钨钛薄膜的制备方法
公开(公告)号：US5916855A
公开(公告)日：1999-06-29
申请号：US829704
申请日：1997-03-26
申请人： Steven C. Avanzino , Christy Mei-Chu Woo , Diana Marie Schonauer , Peter Austin Burke
发明人： Steven C. Avanzino , Christy Mei-Chu Woo , Diana Marie Schonauer , Peter Austin Burke
IPC分类号： C09G1/02 , C09K3/14 , H01L21/321 , H01L21/3105 , H01L21/306
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/3212
摘要： A polishing slurry composition and its method of making for planarization of silicon semiconductor wafers by chemical mechanical polishing of the wafer. A slurry formulation utilizing a ferric salt tungsten oxidizer, an ammonium persulfate titanium oxidizer, a fatty acid suspension agent, alumina particles with a small diameter and tight diameter range, coated with a solubility coating, and a chemical stabilizer, provides high tungsten and titanium polish rates with high selectivity to silicon dioxide, and good oxide defectivity for use in tungsten local interconnect applications. A method for making a tungsten slurry includes first thoroughly blending small diameter alumina particles with a tight diameter range in an aqueous concentrate with a suspension agent, then mixing with water and oxidizers. Ferric salt tungsten slurries made by this method provide excellent tungsten polish characteristics for via plug and local interconnect applications.
摘要翻译：抛光浆料组合物及其通过晶片的化学机械抛光来制造硅半导体晶片的平面化的方法。使用三价铁钨氧化剂，过硫酸铵钛氧化剂，脂肪酸悬浮剂，小直径和紧密直径范围的氧化铝颗粒，涂覆有溶解度涂层和化学稳定剂的浆料配方提供高钨和钛抛光对二氧化硅具有高选择性的速率，以及用于钨局部互连应用的良好的氧化物缺陷率。一种制备钨浆料的方法包括首先用具有悬浮剂的含水浓缩物中将紧密直径范围的小直径氧化铝颗粒充分混合，然后与水和氧化剂混合。通过该方法制备的铁盐钨浆通过插塞和局部互连应用提供优异的钨酸盐抛光特性。

65. 发明授权

US07084062B1 Use of Ta-capped metal line to improve formation of memory element films 有权
标题翻译：使用钽盖金属线改善记忆元素膜的形成
公开(公告)号：US07084062B1
公开(公告)日：2006-08-01
申请号：US11033653
申请日：2005-01-12
申请人： Steven C. Avanzino , Amit P. Marathe
发明人： Steven C. Avanzino , Amit P. Marathe
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76852 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/146 , H01L45/16
摘要： Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor substrate where vias are to be placed, recess etching the mask substantially in all upper surfaces except where vias are to be placed, depositing a Ta-containing capping layer over substantially all the metal line surfaces except the surface where vias are to be placed, polishing the Ta-containing capping layer to produce a damascened Ta-containing cap while exposing the metal line at the via forming surface, depositing a dielectric layer, patterning the dielectric layer to form a via to expose a portion of the metal line, and depositing memory element films. The improved Ta—Cu interface of the subject invention mitigates and/or eliminates lateral growth of memory element films and copper voiding under the dielectric layer at the top surface of the metal line, and thereby enhances reliability and performance of semiconductor devices.
摘要翻译：公开了用于沉积用于半导体器件的改进的存储元件膜的方法。所述方法包括在要放置通孔的半导体衬底的金属线的上表面上提供硬掩模，基本上在除了要放置通孔之外的所有上表面中蚀刻掩模，沉积含Ta的覆盖层在除了要放置通孔的表面之外的基本上所有的金属线表面上，抛光含Ta的封盖层，以在露出金属线在通孔形成表面的同时产生一个镶嵌的含Ta盖，沉积介电层，电介质层以形成通孔以暴露金属线的一部分，以及沉积存储元件膜。本发明的改进的Ta-Cu界面缓和了和/或消除了金属线顶表面下的介质层下存储元件膜的横向生长和铜空隙化，从而提高了半导体器件的可靠性和性能。

66. 发明授权

US06989604B1 Conformal barrier liner in an integrated circuit interconnect 有权
标题翻译：集成电路互连中的保形阻挡衬垫
公开(公告)号：US06989604B1
公开(公告)日：2006-01-24
申请号：US10672103
申请日：2003-09-26
申请人： Christy Mei-Chu Woo , Minh Van Ngo , John E. Sanchez, Jr. , Steven C. Avanzino
发明人： Christy Mei-Chu Woo , Minh Van Ngo , John E. Sanchez, Jr. , Steven C. Avanzino
IPC分类号： H01L23/52
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76871 , H01L21/76876 , H01L2221/1089
摘要： An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.
摘要翻译：一种在其上具有基板和半导体器件的集成电路。衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

67. 发明授权

US06841473B1 Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap 有权
标题翻译：制造具有低溶解度金属导体互连帽的集成电路
公开(公告)号：US06841473B1
公开(公告)日：2005-01-11
申请号：US10672126
申请日：2003-09-26
申请人： Pin-Chin Connie Wang , Steven C. Avanzino
发明人： Pin-Chin Connie Wang , Steven C. Avanzino
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76849 , H01L21/76855 , H01L21/76858 , H01L21/76862 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.
摘要翻译：提供了一种具有半导体器件的半导体衬底的集成电路的制造方法。形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有形成在其中的开口。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。铈导体互连帽设置在导电芯上方，在电介质层和铈导体互连帽上方具有覆盖层。

68. 发明授权

US06808591B1 Model based metal overetch control 有权
标题翻译：基于型号的金属防腐控制
公开(公告)号：US06808591B1
公开(公告)日：2004-10-26
申请号：US10021531
申请日：2001-12-12
申请人： Khoi A. Phan , Bharath Rangarajan , Christopher F. Lyons , Steven C. Avanzino , Ramkumar Subramanian , Bhanwar Singh , Cyrus E. Tabery
发明人： Khoi A. Phan , Bharath Rangarajan , Christopher F. Lyons , Steven C. Avanzino , Ramkumar Subramanian , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： H01L21302
CPC分类号： H01L21/67253 , H01L21/32136
摘要： A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch characterization. An overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system.
摘要翻译：提供了用于金属过程控制的系统和方法。通过利用过滤设备模型来确定金属过蚀刻过程以确定过蚀刻时间或过程延伸端点。系统和方法减少了手动测试和手动过程表征的需要。一种过蚀系统包括金属蚀刻机，目标装置和过程控制器。目标设备位于金属蚀刻机中或其上。该过程控制器耦合到金属蚀刻器。过程控制器通过金属蚀刻器控制目标器件的过蚀刻。该过程控制器包括一个过时延时间控制器，一组蚀刻控制模型和一个控制系统。

69. 发明授权

US06723635B1 Protection low-k ILD during damascene processing with thin liner 有权
标题翻译：保护低k ILD在镶嵌加工与薄衬里
公开(公告)号：US06723635B1
公开(公告)日：2004-04-20
申请号：US10115245
申请日：2002-04-04
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76807
摘要： Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
摘要翻译：通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用铜。

70. 发明授权

US06682978B1 Integrated circuit having increased gate coupling capacitance 有权
标题翻译：具有增加的栅极耦合电容的集成电路
公开(公告)号：US06682978B1
公开(公告)日：2004-01-27
申请号：US09504087
申请日：2000-02-15
申请人： Stephen Keetai Park , Steven C. Avanzino
发明人： Stephen Keetai Park , Steven C. Avanzino
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention is directed to an integrated circuit having an increased gate coupling capacitance. The integrated circuit includes a substrate having a surface, the substrate having a trench extending below the surface. A trench fill material is disposed in the trench and has a portion extending above the surface. A first conductive layer is adjacent the trench fill material and has a portion extending over the portion of the insulative material. An insulative layer is adjacent the first conductive layer and a second conductive layer is adjacent the insulative layer. The present invention further is directed to a method of fabricating an integrated circuit on a substrate including the steps of forming a trench in the substrate, the trench extending below a surface of the substrate; providing a trench fill material in the trench such that the trench fill material extends above the surface of the substrate; and providing a first conductive layer over at least a portion of the trench fill material.
摘要翻译：本发明涉及具有增加的栅极耦合电容的集成电路。集成电路包括具有表面的衬底，衬底具有在表面下方延伸的沟槽。沟槽填充材料设置在沟槽中并且具有在表面上方延伸的部分。第一导电层与沟槽填充材料相邻并且具有在绝缘材料的一部分上延伸的部分。绝缘层与第一导电层相邻，第二导电层与绝缘层相邻。本发明还涉及一种在衬底上制造集成电路的方法，包括以下步骤：在衬底中形成沟槽，沟槽延伸到衬底的表面下方; 在所述沟槽中提供沟槽填充材料，使得所述沟槽填充材料在所述衬底的表面上方延伸; 以及在所述沟槽填充材料的至少一部分上提供第一导电层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式