专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07515479B2 Nonvolatile semiconductor storage device and method for writing therein 有权
标题翻译：非易失性半导体存储装置及其写入方法
公开(公告)号：US07515479B2
公开(公告)日：2009-04-07
申请号：US10598853
申请日：2005-11-01
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
IPC分类号： G11C11/34
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译：通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行位数据写入。当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

62. 发明申请

US20070132080A1 Semiconductor chip mounted interposer, semiconductor device, semiconductor chip interposer fabrication method, bare chip mounted interposer, and interposer sheet 审中-公开
标题翻译：半导体芯片安装的内插器，半导体器件，半导体芯片插入器制造方法，裸芯片安装的插入器和插入片
公开(公告)号：US20070132080A1
公开(公告)日：2007-06-14
申请号：US10595424
申请日：2003-12-15
申请人： Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
发明人： Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
IPC分类号： H01L23/02
CPC分类号： H01L23/3135 , H01L23/3128 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2225/0651 , H01L2225/06513 , H01L2225/0652 , H01L2225/06572 , H01L2225/06582 , H01L2225/06596 , H01L2924/00014 , H01L2924/01004 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.
摘要翻译：半导体芯片安装插入件（60）通过在半导体芯片（50）和插入件（20）之间执行引线键合而构成，其中连接到芯片（50）的端子（51）的端子（21）和分离的端子（22）形成在插入件（20）的上表面上。半导体芯片（30）安装在封装基板（10）的顶面上，插入件（60）粘接到芯片（30）的上部，并且在端子（22）和端子（11'）。当以这种方式配置具有组合成一个封装的多个半导体芯片的半导体器件时，可以容易地保证每个半导体芯片的KGD（Known-Good-Die），并且可以以高产量的良好单元制造半导体器件。此外，半导体芯片可以原样使用，而不限制其端子的位置，间距，信号布置等。

63. 发明申请

US20050169050A1 Semiconductor device with a metal insulator semiconductor transistor 审中-公开
标题翻译：具有金属绝缘体半导体晶体管的半导体器件
公开(公告)号：US20050169050A1
公开(公告)日：2005-08-04
申请号：US11052142
申请日：2005-02-08
申请人： Yasuyoshi Itoh , Shuuichi Ueno , Haruo Furuta , Natsuo Ajika
发明人： Yasuyoshi Itoh , Shuuichi Ueno , Haruo Furuta , Natsuo Ajika
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L29/66833 , H01L21/26586 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/42352 , H01L29/42368 , H01L29/513 , H01L29/66545 , H01L29/66583 , H01L29/7833 , H01L29/7923
摘要： It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TR1) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.
摘要翻译：本发明的目的是提供一种能够在非易失性存储器的缩放进行时能够在一个存储单元中保持多位信息的半导体器件，以及半导体器件的制造方法。沟槽（TR 1）形成在MONOS晶体管的沟道部分中。然后，使位于沟槽（TR1）的栅极绝缘膜（120）的氮化硅膜（122）中的源极侧部分和漏极侧部分作为能够保持的第一和第二电荷保持部电荷（CH 1）和（CH 2）。在电荷（CH 1）被捕获并且电荷（CH 2）然后被捕获的情况下，因此，沟槽（TR 1）中的栅电极（130）的部分（130a）用作一个盾牌如果向栅电极（130）施加固定电位，则第二电荷保持部不受电荷（CH 1）引起的电场（EF 1）的影响，使得电荷（CH 2）不被抑制。

64. 发明授权

US5994732A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5994732A
公开(公告)日：1999-11-30
申请号：US852817
申请日：1997-05-07
申请人： Natsuo Ajika , Akinori Matsuo
发明人： Natsuo Ajika , Akinori Matsuo
IPC分类号： H01L21/8247 , G11C16/16 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/16
摘要： A nonvolatile semiconductor memory device has a plurality of p well regions in a memory cell array region. P well region is independently provided for each erase block. Each p well region is connected to a common well/source line driver, respectively. Well/source line driver is connected to a well/source power supply and a well/block decoder. Therefore, a nonvolatile semiconductor memory device which can inhibit a well disturbance in erase operation can be provided.
摘要翻译：非易失性半导体存储器件在存储单元阵列区域中具有多个p阱区域。独立地为每个擦除块提供P阱区。每个p阱区分别连接到公共阱/源极线驱动器。阱/源极线驱动器连接到阱/源电源和阱/块解码器。因此，可以提供可以抑制擦除操作中的良好干扰的非易失性半导体存储器件。

65. 发明授权

US5659505A Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor 失效
标题翻译：电可编程和可擦除的非易失性半导体存储器件及其操作方法
公开(公告)号：US5659505A
公开(公告)日：1997-08-19
申请号：US509250
申请日：1995-07-31
申请人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda
发明人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda
IPC分类号： G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , G11C11/40
CPC分类号： H01L27/11517 , G11C16/0408 , G11C16/0416 , G11C16/16 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7883
摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.
摘要翻译：在擦除时，电子同时从多个存储单元的源中注入到浮动栅极中。因此，多个存储单元的阈值电压增加。在编程中，电子从所选择的存储单元的浮动栅极发射到漏极。因此，所选存储单元的阈值电压降低。

66. 发明授权

US5554867A Nonvolatile semiconductor memory device having a memory cell transistor and a select transistor 失效
标题翻译：具有存储单元晶体管和选择晶体管的非易失性半导体存储器件
公开(公告)号：US5554867A
公开(公告)日：1996-09-10
申请号：US352656
申请日：1994-12-09
申请人： Natsuo Ajika , Atsushi Ohba
发明人： Natsuo Ajika , Atsushi Ohba
IPC分类号： H01L21/8247 , G11C7/18 , G11C16/04 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68
CPC分类号： G11C16/0416 , G11C7/18 , H01L27/115
摘要： A nonvolatile semiconductor memory device is provided including a DINOR (Divided Bit Line NOR) type cell that allows further reduction of the cell size while ensuring immunity from drain-disturb. In the nonvolatile semiconductor memory device, a sub-bit line is formed to have a length corresponding to the length of 16-1024 memory cell transistors. Memory cell transistors corresponding to the length of that sub-bit line are connected to the sub-bit line. Thus, the effective cell size is reduced while ensuring immunity from drain-disturb.
摘要翻译：提供了包括DINOR（分频位线NOR）型电池的非易失性半导体存储器件，其允许进一步降低电池尺寸，同时确保针对漏极干扰的抗扰性。在非易失性半导体存储器件中，子位线形成为具有与16-1024个存储单元晶体管的长度对应的长度。对应于该子位线的长度的存储单元晶体管连接到子位线。因此，有效的电池尺寸减小，同时确保免受漏极干扰的影响。

67. 发明授权

US5444282A Semiconductor device and a method of manufacturing thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5444282A
公开(公告)日：1995-08-22
申请号：US268877
申请日：1994-06-30
申请人： Yasuo Yamaguchi , Natsuo Ajika , Tsuyoshi Yamano
发明人： Yasuo Yamaguchi , Natsuo Ajika , Tsuyoshi Yamano
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/762 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/786 , H01L27/01 , H01L23/48 , H01L27/02 , H01L29/10
CPC分类号： H01L29/66772 , H01L21/76264 , H01L29/41733 , H01L29/458 , H01L29/78621 , H01L21/76267 , H01L21/76281 , H01L2924/0002 , Y10S257/90
摘要： A semiconductor device of a field effect transistor having an SOI structure is formed as below. Using a gate electrode 20 as a mask, n type impurities are implanted into an SOI layer of p type to form additional source/drain regions of intermediate concentration. Then, a relatively thin sidewall spacer is formed at the sidewall of the gate electrode. Using the sidewall spacer as a mask, a titanium silicide layer is formed in self-alignment on the surface of the SOI layer. Next, a relatively thick sidewall spacer is formed. Using this sidewall spacer as a mask, n type impurities are implanted to form a source/drain region of high concentration. According to this manufacturing step, over-etching of the source/drain region are prevented in performing anisotropic etching at the time of sidewall spacer formation.
摘要翻译：如下形成具有SOI结构的场效晶体管的半导体器件。使用栅电极20作为掩模，将n型杂质注入到p型SOI层中以形成中等浓度的附加源/漏区。然后，在栅电极的侧壁处形成相对薄的侧壁间隔物。使用侧壁间隔物作为掩模，在SOI层的表面上自对准地形成硅化钛层。接下来，形成相对较厚的侧壁间隔物。使用该侧壁间隔物作为掩模，注入n型杂质以形成高浓度的源极/漏极区域。根据该制造步骤，在侧壁间隔物形成时，在进行各向异性蚀刻时，防止了源极/漏极区域的过度蚀刻。

68. 发明授权

US5400278A Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5400278A
公开(公告)日：1995-03-21
申请号：US114229
申请日：1993-09-01
申请人： Yuichi Kunori , Natsuo Ajika , Hiroshi Onoda , Makoto Ohi , Atsushi Fukumoto
发明人： Yuichi Kunori , Natsuo Ajika , Hiroshi Onoda , Makoto Ohi , Atsushi Fukumoto
IPC分类号： H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/11517 , H01L27/11526
摘要： In a semiconductor memory device according to the present invention, a conductive layer is formed on a field oxide film in a boundary region on the main surface of a semiconductor substrate. A floating gate electrode, an interlayer insulating film, and a control gate electrode are formed on the semiconductor substrate in a memory cell array region with a gate insulating film interposed therebetween. A gate electrode is formed in a peripheral circuit region with the gate insulating film interposed therebetween. An interlayer insulating film is formed on the conductive layer, the gate electrode, and the control gate electrode. A contact hole is formed at a predetermined position of the interlayer insulating film. An interconnection layer is selectively formed on the interlayer insulating film including the inner surface of the contact hole. According to the present invention, it is possible to prevent formation of a concave portion on the surface of the field oxide film in the boundary region. It is also possible to protect the memory cell array region from an external noise by forming the conductive layer on the field oxide film in the boundary region and by fixing the potential of the conductive layer.
摘要翻译：在根据本发明的半导体存储器件中，在半导体衬底的主表面上的边界区域中的场氧化物膜上形成导电层。在半导体衬底上形成有一个栅极绝缘膜和一个控制栅电极的存储单元阵列区域中，栅极绝缘膜插在其间。栅极电极形成在外围电路区域中，栅极绝缘膜插入其间。在导电层，栅电极和控制栅电极上形成层间绝缘膜。在层间绝缘膜的预定位置处形成接触孔。在包括接触孔的内表面的层间绝缘膜上选择性地形成布线层。根据本发明，可以防止在边界区域的场氧化膜的表面上形成凹部。也可以通过在边界区域的场氧化膜上形成导电层，并通过固定导电层的电位来保护存储单元阵列区域免受外部噪声的影响。

69. 发明授权

US5355022A Stacked-type semiconductor device 失效
标题翻译：叠层型半导体器件
公开(公告)号：US5355022A
公开(公告)日：1994-10-11
申请号：US936390
申请日：1992-08-28
申请人： Kazuyuki Sugahara , Natsuo Ajika , Toshiaki Ogawa , Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Kazuyuki Sugahara , Natsuo Ajika , Toshiaki Ogawa , Toshiaki Iwamatsu , Takashi Ipposhi
IPC分类号： H01L27/00 , H01L21/02 , H01L21/20 , H01L21/762 , H01L21/822 , H01L27/12 , H01L29/78 , H01L29/786 , H01L27/02 , H01L23/48
CPC分类号： H01L21/2007 , H01L21/76251 , H01L21/8221 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896
摘要： In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700.degree. C. or below and changing the refractory metal layer to silicide.
摘要翻译：在叠层型半导体器件的制造方法中，首先，在层间绝缘层上形成有具有形成在其上的第一器件的第一半导体衬底，层间绝缘层形成平坦化的多晶硅层。将第一半导体衬底和第二半导体衬底通过将多晶硅层的表面与形成在第二半导体衬底上的难熔金属层的表面紧密接触，在700℃以下进行热处理，将难熔金属层改为硅化物。

70. 发明授权

US5240872A Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions 失效
标题翻译：制造具有接触源极/漏极区域的互连层的半导体器件的方法
公开(公告)号：US5240872A
公开(公告)日：1993-08-31
申请号：US925148
申请日：1992-08-06
申请人： Kaoru Motonami , Natsuo Ajika , Atsushi Hachisuka , Yoshinori Okumura , Yasushi Matsui
发明人： Kaoru Motonami , Natsuo Ajika , Atsushi Hachisuka , Yoshinori Okumura , Yasushi Matsui
IPC分类号： H01L21/8242 , H01L23/485 , H01L27/108
CPC分类号： H01L27/10873 , H01L23/485 , H01L27/10817 , H01L2924/0002
摘要： A semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.
摘要翻译：半导体器件包括MOS型场效应晶体管，其栅极（4）的表面被第一绝缘膜（5）覆盖，左右侧设置有一对第二绝缘膜（10）。第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面（4）。至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式