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61. 发明申请

US20070241424A1 VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：使用间隔型电极的垂直平行平板电容器及其制造方法
公开(公告)号：US20070241424A1
公开(公告)日：2007-10-18
申请号：US11279434
申请日：2006-04-12
申请人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
发明人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
IPC分类号： H01L29/00
CPC分类号： H01G4/33 , H01G4/236 , H01L28/91 , Y10T29/435
摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalks of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalks of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalks of the aperture is vertical and separated by a second pair of opposite sidewalks that is outward sloped.
摘要翻译：电容器结构使用位于电介质层内的开口依次位于衬底上。嵌入电介质层内的一对导体互连层终止于孔的一对相对的人行道。一对电容器板位于孔的一对相对的人行道上，并接触一对导体互连层，但不填充孔。电容器介质层位于一对电容器板之间并填充孔。可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的人行道是垂直的并且被向外倾斜的第二对相对的人行道分隔开时。

62. 发明申请

US20070164357A1 Structure and method for MOSFET gate electrode landing pad 有权
标题翻译： MOSFET栅极电极着陆焊盘的结构和方法
公开(公告)号：US20070164357A1
公开(公告)日：2007-07-19
申请号：US11333068
申请日：2006-01-17
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

63. 发明申请

US20070148958A1 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US20070148958A1
公开(公告)日：2007-06-28
申请号：US11499220
申请日：2006-08-04
申请人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

64. 发明申请

US20070117313A1 MIM CAPACITOR AND METHOD OF FABRICATING SAME 有权
标题翻译： MIM电容器及其制造方法
公开(公告)号：US20070117313A1
公开(公告)日：2007-05-24
申请号：US11625883
申请日：2007-01-23
申请人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Louis Hsu
发明人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Louis Hsu
IPC分类号： H01L21/8242 , H01L29/94 , H01L27/108
CPC分类号： H01L23/5223 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a MIM capacitor comprising a conformal conductive liner formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer formed over a top surface of the conformal conductive liner; and a second plate of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.
摘要翻译：一种镶嵌MIM电容器和一种制造MIM电容器的方法。 MIN电容器包括具有顶表面和底表面的电介质层; 电介质层中的沟槽，沟槽从电介质层的顶表面延伸到底表面; MIM电容器的第一板包括形成在所有侧壁上并沿着沟槽的底部延伸的共形导电衬垫，沟槽的底部与电介质层的底表面共面; 绝缘层，形成在所述共形导电衬垫的顶表面上; 以及MIM电容器的第二板，其包括与所述绝缘层直接物理接触的芯导体，所述芯导体填充所述沟槽中的未被所述共形导电衬垫和所述绝缘层填充的空间。该方法包括与镶嵌互连线同时形成MIM电容器的部分。

65. 发明申请

US20060267208A1 Method of forming closed air gap interconnects and structures formed thereby 失效
标题翻译：形成闭合气隙互连件和由此形成的结构的方法
公开(公告)号：US20060267208A1
公开(公告)日：2006-11-30
申请号：US11405283
申请日：2006-04-17
申请人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
发明人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.
摘要翻译：描述了形成闭合气隙互连结构的方法。在互连线下方由永久支撑电介质的区域构成的起始结构和在互连结构的其余部分中存在的具有一个或多个牺牲电介质的周围的互连通孔被封装有电介质阻挡层，其使用具有规则的模板孔阵列然后通过电介质阻挡层中的孔提取牺牲电介质，使得互连线基本上被除了线下方的支撑电介质的区域之外的空气包围。通过沉积第二阻挡电介质来封闭盖层中的孔，从而形成封闭的气隙。描述该方法的几个实施例和所得到的结构。

66. 发明申请

US20060234497A1 Interconnect structure and method of fabrication of same 失效
公开(公告)号：US20060234497A1
公开(公告)日：2006-10-19
申请号：US11107074
申请日：2005-04-15
申请人： Chih-Chao Yang , Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Meeyoung Yoon
发明人： Chih-Chao Yang , Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Meeyoung Yoon
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

67. 发明申请

US20060183308A1 Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gases additions 失效
标题翻译：使用含碳气体添加剂蚀刻双预掺杂多晶硅栅极叠层的方法
公开(公告)号：US20060183308A1
公开(公告)日：2006-08-17
申请号：US10730891
申请日：2003-12-10
申请人： Ying Zhang , Timothy Dalton , Wesley Natzle
发明人： Ying Zhang , Timothy Dalton , Wesley Natzle
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L21/28123 , H01L21/32137 , H01L21/32139
摘要： A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and etching by exposing the conductive layer to an etching composition comprising at least one carbon containing gas. The carbon containing gas can be selected from gases having the general formula CxHy, such as, for example, CH4, C2H2, C2H4, and C2H6. The carbon containing gas can further be selected from gases having the general formula CxHyA, wherein a can represent one or more additional substituents selected from O, N, P, S, F, Cl, Br, and I. The processes can result in dual pre-doped gate stacks having essentially vertical sidewalls and further having a width of at least about 3 nm, such as from about 5 nm to about 150 nm.
摘要翻译：提供了在半导体应用中使用诸如互补金属氧化物半导体（CMOS）器件和金属氧化物半导体场效应晶体管（MOSFET）的双预预掺杂栅叠层的方法。该方法包括在栅叠层上提供至少一个预先掺杂的导电层，例如多晶硅（poly-Si），以及通过将导电层暴露于含有至少一种含碳气体的蚀刻组合物进行蚀刻。含碳气体可以选自具有通式C x H H y H的气体，例如CH 4，C 3， H 2 H 2，C 2 H 4，和C 2 H 2， 6 。含碳气体还可以选自具有通式C x H A A A的气体，其中a可以表示一个或多个选自O，N，P ，S，F，Cl，Br和I.该工艺可以导致具有基本上垂直的侧壁并且还具有至少约3nm，例如约5nm至约150nm的宽度的双预掺杂栅叠层。

68. 发明申请

US20060043435A1 Nano-scaled gate structure with self-interconnect capabilities 失效
公开(公告)号：US20060043435A1
公开(公告)日：2006-03-02
申请号：US10930989
申请日：2004-08-31
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/28114 , H01L21/76895 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/0629 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545
摘要： Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.

69. 发明申请

US20050230831A1 Structure to improve adhesion between top CVD low-k dielectiric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低k介电层和介电顶盖层之间的粘附
公开(公告)号：US20050230831A1
公开(公告)日：2005-10-20
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/312 , H01L21/316 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/532
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

70. 发明授权

US08471306B2 Double-sided integrated circuit chips 失效
标题翻译：双面集成电路芯片
公开(公告)号：US08471306B2
公开(公告)日：2013-06-25
申请号：US13192608
申请日：2011-07-28
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/80 , H01L29/04 , H01L31/036
CPC分类号： G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译：双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。下晶片可以包括布线水平。下部晶片可以包括用于触点的着陆焊盘。与下晶片的硅层的接触可以被硅化。

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