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    • 61. 发明申请
    • MRAM cell structure and method of fabrication
    • MRAM单元结构及其制造方法
    • US20050260773A1
    • 2005-11-24
    • US10849311
    • 2004-05-19
    • Liubo HongTom ZhongLin Yang
    • Liubo HongTom ZhongLin Yang
    • G11C11/16H01L21/00H01L27/22H01L43/12
    • G11C11/16H01L27/222H01L43/12
    • An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key feature in the method of forming the MRAM cell structure is a two step planarization of an insulation layer deposited on the MTJ array. A CMP step flattens the insulation layer at a distance about 60 to 200 Angstroms above the cap layer in the MTJ. Then an etch back step thins the insulation layer to a level about 50 to 190 Angstroms below the top of the cap layer. Less than 5 Angstroms of the cap layer is removed. The distance variation from the free layer to an overlying bit line or word line is within +/−5 Angstroms.
    • 公开了一种MRAM结构,其中从位线或字线到MTJ中的下游自由层的距离小且受到良好控制。 因此,位线或字线切换电流减少并且分布紧密,从而更好的器件性能。 形成MRAM单元结构的方法中的一个关键特征是沉积在MTJ阵列上的绝缘层的两步平面化。 CMP步骤在MTJ的帽层上方约60至200埃的距离处使绝缘层平坦化。 然后,回蚀步骤将绝缘层沉降到帽层顶部下方约50至190埃的水平。 少于5埃的盖层被去除。 从自由层到上位线或字线的距离变化在+/- 5埃以内。
    • 63. 发明授权
    • Plasma vapor deposition with coil sputtering
    • 等离子体气相沉积与线圈溅射
    • US06695954B2
    • 2004-02-24
    • US09977160
    • 2001-10-11
    • Liubo Hong
    • Liubo Hong
    • C23C1434
    • H01J37/32082H01J37/3408
    • A method and apparatus for depositing a layer of a material which contains a metal on a workpiece surface, in an installation including a deposition chamber; a workpiece support providing a workpiece support surface within the chamber; a coil within the chamber, the coil containing the metal that will be contained in the layer to be deposited; and an RF power supply connected to deliver RF power to the coil in order to generate a plasma within the chamber, a DC self bias potential being induced in the coil when only RF power is delivered to the coil. A DC bias potential which is different in magnitude from the DC self bias potential is applied to the coil from a DC voltage source. In order to place a deposition chamber of a physical vapor deposition apparatus in which metal or other material is sputtered from a target and a coil in condition to effect deposition of a layer consisting of the sputtered material on a substrate subsequent to deposition, in the apparatus, of a layer containing a reaction compound of the sputtered material, the chamber is filled with a non-reactive gas and a voltage is applied to sputter from the target and coil any reaction compound which has coated the target and coil during deposition of the layer containing the reaction compound of the sputtered metal.
    • 一种用于在包括沉积室的装置中沉积在工件表面上含有金属的材料层的方法和装置; 工件支撑件,其在所述腔室内提供工件支撑表面; 在该腔室内的线圈,该线圈包含将被包含在待沉积层中的金属; 以及RF电源,其被连接以将RF功率提供给线圈以便在腔室内产生等离子体,当只有RF功率被传送到线圈时,在线圈中感应出DC自偏压电位。 从直流电压源向线圈施加与DC自偏压电位不同的直流偏置电位。为了放置物理气相沉积设备的沉积室,其中金属或其他材料从目标溅射 以及在该装置中沉积包含溅射材料的反应化合物的层的条件下,使由溅射材料组成的层沉积在基板上的条件的线圈,所述室填充有非反应性气体,并且 施加电压从目标物溅射并卷绕在包含溅射金属的反应化合物的层的沉积期间涂覆了目标物和线圈的任何反应化合物。
    • 65. 发明授权
    • Write head having a dry-etchable antireflective intermediate layer
    • 写头具有可干蚀刻的抗反射中间层
    • US06369983B1
    • 2002-04-09
    • US09374591
    • 1999-08-13
    • Liubo Hong
    • Liubo Hong
    • G11B531
    • G11B5/3163G11B5/3116G11B5/313G11B5/3133
    • A method and system for providing a write head is disclosed. The write head includes at least one pole and an insulating layer. The at least one pole is for writing magnetic data. The method and system include providing an intermediate layer and providing at least one conductive coil. The intermediate layer is disposed between the insulating layer and the at least one conductive coil. The intermediate layer is composed of at least one material capable of being dry etched. The at least one conductive coil is in proximity to the at least one pole and is for carrying a current to energize the at least one pole during writing.
    • 公开了一种用于提供写入头的方法和系统。 写头包括至少一个极和绝缘层。 至少一个磁极用于写磁数据。 该方法和系统包括提供中间层并提供至少一个导电线圈。 中间层设置在绝缘层和至少一个导电线圈之间。 中间层由能够被干蚀刻的至少一种材料构成。 所述至少一个导电线圈靠近所述至少一个极,并且用于承载电流以在写入期间激励所述至少一个极。
    • 68. 发明授权
    • Magnetoresistive device with a hard bias capping layer
    • 具有硬偏压盖层的磁阻器件
    • US08614864B1
    • 2013-12-24
    • US13467354
    • 2012-05-09
    • Liubo HongHonglin Zhu
    • Liubo HongHonglin Zhu
    • G11B5/39
    • H01L43/12H01L43/08
    • A magnetoresistive device is provided. The device includes at least one magnetoresistive element having at least one side, at least one hard bias layer in proximity to the at least one side of the at least one magnetic element, and a hard bias capping structure on the at least one hard bias layer. The hard bias capping structure includes a protective layer covering at least a first portion of the at least one hard bias layer and a planarization stop layer covering a second portion of the at least one hard bias layer. A portion of the protective layer resides between the planarization stop layer and the at least one hard bias layer.
    • 提供了一种磁阻器件。 该器件包括至少一个具有至少一个侧面的磁阻元件,在至少一个磁性元件的至少一个侧面附近的至少一个硬偏置层,以及在该至少一个硬偏置层上的硬偏压封盖结构 。 所述硬偏压封盖结构包括覆盖所述至少一个硬偏置层的至少第一部分的保护层和覆盖所述至少一个硬偏置层的第二部分的平坦化停止层。 保护层的一部分位于平坦化停止层和至少一个硬偏压层之间。
    • 69. 发明授权
    • Spacer structure in MRAM cell and method of its fabrication
    • MRAM单元的间隔结构及其制作方法
    • US08422276B2
    • 2013-04-16
    • US12930955
    • 2011-01-20
    • Jun YuanLiubo HongMao-Min Chen
    • Jun YuanLiubo HongMao-Min Chen
    • G11C11/00
    • H01L43/12H01L27/222H01L43/08
    • Methods are presented for fabricating an MTJ element having a uniform vertical distance between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each method forms a dielectric spacer layer on the lateral sides of the MTJ element and, depending on the method, includes an additional layer that protects the spacer layer during etching processes used to form a Cu damascene bit line. At various stages in the process, a dielectric layer is also formed to act as a CMP stop layer so that the capping layer on the MTJ element is not thinned by the CMP process that planarizes the surrounding insulation. Subsequent to planarization, the stop layer is removed by an anisotropic etch of such precision that the MTJ element capping layer is not reduced in thickness and serves to maintain uniform vertical distance between the bit line and the MTJ free layer.
    • 提出了用于制造在其自由层和位线之间具有均匀垂直距离的MTJ元件的方法,此外,具有邻接MTJ元件的侧面形成的保护间隔层,以消除MTJ层与钻头之间的泄漏电流 线。 每种方法在MTJ元件的侧面上形成电介质间隔层,并且根据该方法,包括在用于形成Cu镶嵌位线的蚀刻工艺期间保护间隔层的附加层。 在该过程的各个阶段,还形成介电层以用作CMP停止层,使得MTJ元件上的覆盖层不会通过使周围绝缘平坦化的CMP工艺变薄。 在平坦化之后,通过各向异性蚀刻去除停止层,其精度使得MTJ元件覆盖层的厚度不减小并用于保持位线和MTJ自由层之间的均匀垂直距离。