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61. 发明申请

US20130067489A1 Power Efficient Callback Patterns 有权
标题翻译：高效回拨模式
公开(公告)号：US20130067489A1
公开(公告)日：2013-03-14
申请号：US13229630
申请日：2011-09-09
申请人： M. David Fields, JR. , Cenk Ergan , Qiang Chen , Michael D. Decker , Kedar Sanjeev Hirve , Walter V. von Koch , Jason J. Weber , Katerina V. Sedova , Karen Elizabeth Parker Anderson
发明人： M. David Fields, JR. , Cenk Ergan , Qiang Chen , Michael D. Decker , Kedar Sanjeev Hirve , Walter V. von Koch , Jason J. Weber , Katerina V. Sedova , Karen Elizabeth Parker Anderson
IPC分类号： G06F3/00 , G06F9/46 , G06F9/44
CPC分类号： G06F9/542 , G06F2209/543 , G06F2209/548
摘要： In one or more embodiments, an application program interface (API) is provided and enables an entity, such as an application, script, or other computing object to register to receive callbacks immediately and, without specifying a time constraint. In this approach, the API does not rely on a timer, such as a system timer. Rather, a non-timer based queue, such as a message queue-type approach is utilized. Specifically, callbacks that are registered through this API can be placed on the message queue and work associated with the registered callback can be performed through the normal course of processing messages and events in the message queue. Over time, such results in a callback pattern that allows an associated web browser and applications such as web applications to remain responsive, while increasing performance and power efficiencies.
摘要翻译：在一个或多个实施例中，提供了一种应用程序接口（API），并使诸如应用程序，脚本或其他计算对象之类的实体能够立即注册以接收回调，并且不指定时间约束。在这种方法中，API不依赖于定时器，例如系统定时器。相反，使用基于非定时器的队列，例如消息队列类型方法。具体来说，通过该API注册的回调可以被放置在消息队列上，并且可以通过处理消息队列中的消息和事件的正常过程来执行与注册的回调相关联的工作。随着时间的推移，这种结果导致回调模式，允许相关联的Web浏览器和应用程序（如Web应用程序）保持响应，同时提高性能和功耗效率。

62. 发明申请

US20120063214A1 Pulse field assisted spin momentum transfer MRAM design 有权
标题翻译：脉冲场辅助自旋动量转移MRAM设计
公开(公告)号：US20120063214A1
公开(公告)日：2012-03-15
申请号：US12807611
申请日：2010-09-09
申请人： Tai Min , Qiang Chen , Po Kang Wang
发明人： Tai Min , Qiang Chen , Po Kang Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/161 , G11C11/1659 , G11C11/1675
摘要： An MRAM array structure and a method of its operation that is not subject to accidental writing on half-selected elements. Each element of the MRAM is an MTJ (magnetic tunneling junction) cell operating in accord with an STT (spin torque transfer) scheme for changing its free layer magnetization state and each cell is patterned to have a C-shape in the horizontal plane. The cell thereby operates by C-mode switching to provide stability against accidental writing by half-selection. During operation, switching of a cell's magnetization is accomplished with the assist of the pulsed magnetic fields of additional word lines that are formed either orthogonal to or parallel to the existing bit lines and that can carry currents in either direction as required to provide the assist.
摘要翻译： MRAM阵列结构及其操作方法，不会在半选择元素上偶然写入。 MRAM的每个元件是根据用于改变其自由层磁化状态的STT（自旋转矩传递）方案操作的MTJ（磁性隧道结）单元，并且每个单元被图案化以在水平面中具有C形。因此，电池通过C模式切换来操作，以通过半选择提供对意外写入的稳定性。在操作期间，通过与现有位线正交或平行的附加字线的脉冲磁场的帮助来实现电池的磁化的切换，并且可以根据需要在任一方向上承载电流以提供辅助。

63. 发明申请

US20110294273A1 Method and Layout of Semiconductor Device with Reduced Parasitics 有权
标题翻译：具有减少寄生性的半导体器件的方法和布局
公开(公告)号：US20110294273A1
公开(公告)日：2011-12-01
申请号：US13087102
申请日：2011-04-14
申请人： Albert Birner , Qiang Chen
发明人： Albert Birner , Qiang Chen
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0661 , H01L29/402 , H01L29/4175 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/4941 , H01L29/7823
摘要： An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.
摘要翻译：公开了一种半导体器件。该器件包括半导体本体，设置在半导体本体上的绝缘材料层以及设置在绝缘材料层上的栅电极材料区域。还包括与栅极区域相邻的源极区域和与栅极区域相邻的漏极区域。栅极连接设置在半导体本体上，其中栅极连接包括将接触区域电耦合到栅电极的栅电极材料区域。绝缘区域设置在栅极连接下方的半导体本体上。

64. 发明授权

US07986008B2 SOI semiconductor components and methods for their fabrication 有权
标题翻译： SOI半导体元件及其制造方法
公开(公告)号：US07986008B2
公开(公告)日：2011-07-26
申请号：US12413185
申请日：2009-03-27
申请人： Ali Icel , Qiang Chen , Mario M. Pelella
发明人： Ali Icel , Qiang Chen , Mario M. Pelella
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823437 , H01L21/823481 , H01L21/84
摘要： SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.
摘要翻译：提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。该部件包括第一导电类型的源区和漏区以及第一半导体层中的第一掺杂浓度。在源区和漏区之间限定第二导电类型的沟道区。栅极绝缘体和栅极电极覆盖沟道区域。第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

65. 发明申请

US20110093830A1 Integrated Circuit Optimization Modeling Technology 有权
标题翻译：集成电路优化建模技术
公开(公告)号：US20110093830A1
公开(公告)日：2011-04-21
申请号：US12771754
申请日：2010-04-30
申请人： Qiang Chen , Sridhar Tirumala , Akash Jain
发明人： Qiang Chen , Sridhar Tirumala , Akash Jain
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/08
摘要： A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target circuit design to produce an indication of susceptibility of the target circuit design to optimization. The model can be produced using Monte Carlo simulations of a set of virtual designs, and fitting a function of said characteristics to the results.
摘要翻译：用于由机器可读文件指定的目标电路设计的设计优化方法包括提供计算机实现的模型，作为由于电路修改过程可实现的电路优化的电路设计的一组特性的函数，例如时间约束栅极长度修改用于泄漏功率降低。使用目标电路设计的所述特征集合的值，将计算机实现的模型应用于目标电路设计以产生目标电路设计的敏感性的指示以进行优化。该模型可以使用一组虚拟设计的蒙特卡罗模拟来生成，并将所述特征的函数拟合到结果中。

66. 发明授权

US07761823B2 Method for adjusting a transistor model for increased circuit simulation accuracy 有权
标题翻译：调整晶体管模型以提高电路仿真精度的方法
公开(公告)号：US07761823B2
公开(公告)日：2010-07-20
申请号：US11803646
申请日：2007-05-15
申请人： Jung-Suk Goo , Qiang Chen
发明人： Jung-Suk Goo , Qiang Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： According to one exemplary embodiment, a method for adjusting a transistor model for increased circuit simulation accuracy includes determining a first gate CD offset by matching a C-V test structure having a normalized channel current to an I-V test structure having the normalized channel current. The method further includes utilizing the first gate CD offset to adjust the transistor model for increased circuit simulation. The method also includes determining a second gate CD offset by varying I-V and C-V gate length parameters in the transistor model to cause simulated data from a test circuit to be approximately equal to measured data from the test circuit. The method further includes utilizing the second gate CD offset to adjust the transistor model.
摘要翻译：根据一个示例性实施例，用于调整用于增加电路仿真精度的晶体管模型的方法包括通过将具有归一化信道电流的C-V测试结构与具有归一化通道电流的I-V测试结构相匹配来确定第一门CD偏移。该方法还包括利用第一栅极CD偏移来调整晶体管模型以增加电路仿真。该方法还包括通过在晶体管模型中改变I-V和C-V栅极长度参数来确定第二栅极CD偏移，以使来自测试电路的模拟数据近似等于来自测试电路的测量数据。该方法还包括利用第二栅极CD偏移来调整晶体管模型。

67. 发明申请

US20090288237A1 Flexible Glove and the Preparation Method Thereof 审中-公开
标题翻译：柔性手套及其制备方法
公开(公告)号：US20090288237A1
公开(公告)日：2009-11-26
申请号：US12126517
申请日：2008-05-23
申请人： Qiang Chen
发明人： Qiang Chen
IPC分类号： A41D19/00 , B29C43/52
CPC分类号： B29C41/14 , A41D19/0058 , B29C41/38
摘要： The present invention relates to a flexible glove prepared from a composition of waterborne polyurethane resin and waterborne acrylic resin, together with a cure-crosslinking agent, to prepare a flexible glove. The flexible glove, prepared by using this specific waterborne resin mixture and the crosslinking agent, after adding one kind of nano-calcium carbonate slurry, have excellent service performance and reasonable preparation cost. During the preparation, 10˜100 portions of waterborne acrylic resin, 0.1˜0.5 portions of amino resin crosslinking agent and 5˜20 portions of nano-calcium carbonate slurry are added to 100 portions of waterborne polyurethane. The present invention also relates to the preparation method of this particular flexible glove.
摘要翻译：本发明涉及由水性聚氨酯树脂和水性丙烯酸树脂组合物与固化交联剂一起制备的柔性手套，以制备柔性手套。通过使用这种特定的水性树脂混合物和交联剂制备的柔性手套，在加入一种纳米碳酸钙浆料后，具有优异的使用性能和合理的制备成本。在制备过程中，将100份水性丙烯酸树脂，0.1〜0.5份氨基树脂交联剂和5〜20份纳米碳酸钙浆料加入到100份水性聚氨酯中。本发明还涉及这种特殊柔性手套的制备方法。

68. 发明授权

US07531403B2 SOI semiconductor components and methods for their fabrication 有权
标题翻译： SOI半导体元件及其制造方法
公开(公告)号：US07531403B2
公开(公告)日：2009-05-12
申请号：US11538001
申请日：2006-10-02
申请人： Ali Icel , Qiang Chen , Mario M. Pelella
发明人： Ali Icel , Qiang Chen , Mario M. Pelella
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823437 , H01L21/823481 , H01L21/84
摘要： SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.
摘要翻译：提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。该部件包括第一半导体层中的第一导电类型和第一掺杂浓度的源区和漏区。在源区和漏区之间限定第二导电类型的沟道区。栅极绝缘体和栅极电极覆盖沟道区域。第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

69. 发明申请

US20080079074A1 SOI SEMICONDUCTOR COMPONENTS AND METHODS FOR THEIR FABRICATION 有权
标题翻译： SOI半导体元件及其制造方法
公开(公告)号：US20080079074A1
公开(公告)日：2008-04-03
申请号：US11538001
申请日：2006-10-02
申请人： Ali Icel , Qiang Chen , Mario M. Pelella
发明人： Ali Icel , Qiang Chen , Mario M. Pelella
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823437 , H01L21/823481 , H01L21/84
摘要： SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.
摘要翻译：提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。该部件包括第一半导体层中的第一导电类型和第一掺杂浓度的源区和漏区。在源区和漏区之间限定第二导电类型的沟道区。栅极绝缘体和栅极电极覆盖沟道区域。第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

70. 发明申请

US20070176727A1 Miniature thin-film bandpass filter 有权
标题翻译：微型薄膜带通滤波器
公开(公告)号：US20070176727A1
公开(公告)日：2007-08-02
申请号：US11345428
申请日：2006-01-31
申请人： Qiang Chen , Hajime Kuwajima
发明人： Qiang Chen , Hajime Kuwajima
IPC分类号： H01F27/28
CPC分类号： H01P1/203
摘要： A bandpass filter includes at least two thin-film layers, a first resonant circuit including a first inductor, and a second resonant circuit including a second inductor. In one embodiment, the first inductor comprises a coil having a counter-clockwise rotation positioned in two or more of the at least two thin-film layers and the second inductor comprises a coil having a clockwise rotation positioned in two or more of the at least two thin-film layer. In this case, the first inductor is coupled to the second inductor in at least one of the at least two thin-film layers when the bandpass filter is energized. In another embodiment, the first inductor has a clockwise rotation and the second has a counter-clockwise rotation positioned. In this case, the first inductor is coupled to the second inductor in at least two of the at least two thin-film layers when the bandpass filter is energized.
摘要翻译：带通滤波器包括至少两个薄膜层，包括第一电感器的第一谐振电路和包括第二电感器的第二谐振电路。在一个实施例中，第一电感器包括具有位于至少两个薄膜层中的两个或更多个中的逆时针旋转的线圈，并且第二电感器包括具有位于至少两个或更多个中的顺时针旋转的线圈两层薄膜层。在这种情况下，当带通滤波器通电时，第一电感器耦合到至少两个薄膜层中的至少一个中的第二电感器。在另一个实施例中，第一电感器具有顺时针旋转，第二电感器具有定位的逆时针旋转。在这种情况下，当带通滤波器通电时，第一电感器耦合到至少两个薄膜层中的至少两个中的第二电感器。

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