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61. 发明申请

US20110225224A1 Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture 有权
标题翻译：在ManArray架构上实现高效的复数乘法和快速傅里叶变换（FFT）
公开(公告)号：US20110225224A1
公开(公告)日：2011-09-15
申请号：US13116332
申请日：2011-05-26
申请人： Nikos P. Pitsianis , Gerald G. Pechanek , Ricardo E. Rodriguez
发明人： Nikos P. Pitsianis , Gerald G. Pechanek , Ricardo E. Rodriguez
IPC分类号： G06F17/14 , G06F7/499
CPC分类号： G06F15/82 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3853 , G06F9/3885 , G06F15/8023 , G06F15/8038 , G06F17/142
摘要： Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.
摘要翻译：提供了复数乘法结果和非常有效的快速傅里叶变换（FFT）的有效计算。采用并行阵列VLIW数字信号处理器以及与计算重叠的处理元件之间的专用复数乘法指令和通信操作，以提供非常高的性能操作。使用紧密封装的VLIW的循环的连续迭代，允许有效地使用复数乘法管线硬件。此外，描述了用于支持组合乘法累加操作的有效技术。

62. 发明申请

US20110219210A1 System Core for Transferring Data Between an External Device and Memory 失效
标题翻译：用于在外部设备和内存之间传输数据的系统核心
公开(公告)号：US20110219210A1
公开(公告)日：2011-09-08
申请号：US13106042
申请日：2011-05-12
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F9/312 , G06F9/30
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

63. 发明申请

US20080301414A1 Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture 有权
标题翻译：在ManArray架构上实现高效的复数乘法和快速傅里叶变换（FFT）
公开(公告)号：US20080301414A1
公开(公告)日：2008-12-04
申请号：US12187746
申请日：2008-08-07
申请人： Nikos P. Pitsianis , Gerald G. Pechanek , Ricardo E. Rodriguez
发明人： Nikos P. Pitsianis , Gerald G. Pechanek , Ricardo E. Rodriguez
IPC分类号： G06F9/302
CPC分类号： G06F15/82 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3853 , G06F9/3885 , G06F15/8023 , G06F15/8038 , G06F17/142
摘要： Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.
摘要翻译：提供了复数乘法结果和非常有效的快速傅里叶变换（FFT）的有效计算。采用并行阵列VLIW数字信号处理器以及与计算重叠的处理元件之间的专用复数乘法指令和通信操作，以提供非常高的性能操作。使用紧密封装的VLIW的循环的连续迭代，允许有效地使用复数乘法管线硬件。此外，描述了用于支持组合乘法累加操作的有效技术。

64. 发明授权

US07072929B2 Methods and apparatus for efficient complex long multiplication and covariance matrix implementation 失效
标题翻译：用于有效复杂长乘法和协方差矩阵实现的方法和装置
公开(公告)号：US07072929B2
公开(公告)日：2006-07-04
申请号：US10004010
申请日：2001-11-01
申请人： Gerald G. Pechanek , Ricardo Rodriguez , Matthew Plonski , David Strube , Kevin Coopman
发明人： Gerald G. Pechanek , Ricardo Rodriguez , Matthew Plonski , David Strube , Kevin Coopman
IPC分类号： G06F7/52
CPC分类号： G06F7/4812 , G06F9/30014 , G06F9/325 , G06F9/3885 , G06F17/15 , G06F17/16 , G06F2207/3896
摘要： A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The multiplier simultaneously performs multiplications to produce each combination of products between the real and imaginary terms of the first and second complex operands. The multiplexer selects which produced products are added to or subtracted from each other based on the type of complex multiplication being performed. The adder simultaneously performs additions and subtractions, if necessary, to produce both real and imaginary results depending on whether the type of complex multiplication being performed is a conjugated operation. The registers store the results of the complex multiplication.
摘要翻译：描述了用于计算各种类型的复数乘法的数字信号处理器。数字信号处理器与寄存器，乘法器，加法器和多路复用器一起操作。寄存器存储第一和第二复数操作数。乘法器同时执行乘法以产生在第一和第二复数操作数的实数和虚数项之间的乘积的每个组合。多路复用器根据正在执行的复数乘法的类型，选择相加或相减的产生的产品。如果需要，加法器同时执行加法和减法，以根据执行的复数乘法是否是共轭运算来产生实数和虚部结果。寄存器存储复数乘法的结果。

65. 发明授权

US06874078B2 Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit 失效
标题翻译：用于使用SISD控制/ SIMD过程模式位执行VLIW单工指令的合并控制/处理元件处理器
公开(公告)号：US06874078B2
公开(公告)日：2005-03-29
申请号：US10620144
申请日：2003-07-15
申请人： Gerald G. Pechanek , Juan G. Revilla
发明人： Gerald G. Pechanek , Juan G. Revilla
IPC分类号： G06F15/16 , G06F9/30 , G06F9/318 , G06F15/173 , G06F15/80 , G06F9/40
CPC分类号： G06F9/3885 , G06F9/3012 , G06F9/30145 , G06F9/30189 , G06F9/3887 , G06F15/17343 , G06F15/8007
摘要： A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed. This structure allows the controlling element in a highly parallel SIMD processor to be reused as one of the processing elements in the array to reduce the overall number of transistors and wires in the SIMD processor while maintaining its capabilities and performance.
摘要翻译：高度并行的数据处理系统包括n个处理元件（PE）和控制器序列处理器（SP）的阵列，其中至少一个PE与控制器SP组合以创建支持两种操作模式的动态合并处理器（DP）。在其第一种操作模式中，DP充当阵列中的PE之一，并参与执行单指令多数据（SIMD）指令。在第二种操作模式中，DP充当PE阵列的控制元件，并执行非阵列指令。为了支持这两种操作模式，DP包括多个执行单元和两个通用寄存器文件。执行单元是“共享的”，因为它们可以在任一操作模式下执行指令。具有非常长的指令字（VLIW）能力，两种操作模式可以在执行的每个VLIW的基础上逐周期生效。这种结构允许高度并行的SIMD处理器中的控制元件被重新用作阵列中的处理元件之一，以在保持其能力和性能的同时减少SIMD处理器中的晶体管和导线的总数。

66. 发明授权

US06868490B1 Methods and apparatus for providing context switching between software tasks with reconfigurable control 失效
标题翻译：用于通过可重新配置的控制在软件任务之间提供上下文切换的方法和装置
公开(公告)号：US06868490B1
公开(公告)日：2005-03-15
申请号：US09598558
申请日：2000-06-21
申请人： Edwin F. Barry , Gerald G. Pechanek , David Carl Strube
发明人： Edwin F. Barry , Gerald G. Pechanek , David Carl Strube
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/46 , G06F15/80
CPC分类号： G06F9/30181 , G06F9/30043 , G06F9/30076 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/462 , G06F15/8007
摘要： The ManArray core indirect VLIW processor consists of an array controller sequence processor (SP) merged with a processing element (PE0) closely coupling the SP with the PE array and providing the capability to share execution units between the SP and PE0. Consequently, in the merged SP/PE0 a single set of execution units are coupled with two independent register files. To make efficient use of the SP and PE resources, the ManArray architecture specifies a bit in the instruction format, the S/P-bit, to differentiate SP instructions from PE instructions. Multiple register contexts are obtained in the ManArray processor by controlling how the array S/P-bit in the ManArray instruction format is used in conjunction with a context switch bit (CSB) for the context selection of the PE register file or the SP register file. In arrays consisting of more than a single PE, the software controllable context switch mechanism is used to reconfigure the array to take advantage of the multiple context support the merged SP/PE provides. For example, a 1×1 can be configured as a 1×1 with context-0 and as a 1×0 with context-1, a 1×2 can be configured as a 1×2 with context-0 and as a 1×1 with context-1, and a 1×5 can be configured as a 1×5 with context-0 and as a 2×2 with context-1. Other array configurations are clearly possible using the present techniques. In the 1×5/2×2 case, the two contexts could be a 1×5 array (context-0) and a 2×2 array (context-1).
摘要翻译： ManArray核心间接VLIW处理器由阵列控制器序列处理器（SP）组成，与处理元件（PE0）合并，该处理元件（PE0）将SP与PE阵列紧密耦合，并提供在SP和PE0之间共享执行单元的能力。因此，在合并的SP / PE0中，单个执行单元集合与两个独立的寄存器文件耦合。为了有效利用SP和PE资源，ManArray架构指定了指令格式（S / P位）中的一位，以区分SP指令和PE指令。通过控制ManArray指令格式中的阵列S / P位如何与用于PE寄存器文件或SP寄存器文件的上下文选择的上下文切换位（CSB）结合使用，在ManArray处理器中获得多个寄存器上下文。在由多个单独的PE组成的阵列中，软件可控上下文切换机制用于重新配置阵列，以利用合并的SP / PE提供的多个上下文支持。例如，1x1可以被配置为具有上下文0的1x1和具有上下文-1的1x0，1x2可以被配置为具有上下文-1的1x2和具有上下文-1的1x1，并且1x5可以被配置为具有上下文-1的1x2 配置为具有上下文0的1x5和具有上下文-1的2x2。使用本技术可以清楚地看出其它阵列配置。在1x5 / 2x2情况下，两个上下文可能是1x5阵列（上下文0）和2x2阵列（上下文-1）。

67. 发明授权

US06845445B2 Methods and apparatus for power control in a scalable array of processor elements 失效
公开(公告)号：US06845445B2
公开(公告)日：2005-01-18
申请号：US09853989
申请日：2001-05-11
申请人： Patrick R. Marchand , Gerald G. Pechanek , Edward A. Wolff
发明人： Patrick R. Marchand , Gerald G. Pechanek , Edward A. Wolff
IPC分类号： G06F1/32 , G06F9/30 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3891 , G06F1/3203 , G06F9/30036 , G06F9/30101 , G06F9/3853 , G06F9/3885
摘要： Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.

68. 发明授权

US06839728B2 Efficient complex multiplication and fast fourier transform (FFT) implementation on the manarray architecture 失效
标题翻译：在Manarray架构上实现高效的复数乘法和快速傅立叶变换（FFT）
公开(公告)号：US06839728B2
公开(公告)日：2005-01-04
申请号：US09337839
申请日：1999-06-22
申请人： Nikos P. Pitsianis , Gerald G. Pechanek , Ricardo E. Rodriguez
发明人： Nikos P. Pitsianis , Gerald G. Pechanek , Ricardo E. Rodriguez
IPC分类号： G06F9/38 , G06F9/30 , G06F15/16 , G06F15/173 , G06F15/80 , G06F17/14 , G06F17/16 , G06F15/00 , G06F7/52
CPC分类号： G06F15/82 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3853 , G06F9/3885 , G06F15/8023 , G06F15/8038 , G06F17/142
摘要： Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

69. 发明授权

US06760831B2 Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 有权
标题翻译：在具有子字执行的基于VLIW的阵列处理器中支持条件执行的方法和装置
公开(公告)号：US06760831B2
公开(公告)日：2004-07-06
申请号：US10114652
申请日：2002-04-01
申请人： Thomas L. Drabenstott , Gerald G. Pechanek , Edwin F. Barry , Charles W. Kurak, Jr.
发明人： Thomas L. Drabenstott , Gerald G. Pechanek , Edwin F. Barry , Charles W. Kurak, Jr.
IPC分类号： G06F1580
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
摘要翻译：使用分层一位，二位或三位编码来定义和编码通用标志（ACF）。每个添加的位提供了先前功能的超集。通过条件组合，可以避免基于复杂条件的顺序一系列条件分支，然后可以将复杂条件用于条件执行。 ACF生成和使用可以由程序员指定。通过改变受影响的标志的数量，条件操作并行性可以被广泛地变化，例如，从VLIW执行中的单处理到八进制处理，以及处理元件（PE）的阵列。多个PE可以同时生成条件信息，程序员能够基于使用处理元件之间的通信接口在不同的处理器中生成的条件来指定一个处理器中的条件执行以传送条件。多处理器阵列中的每个处理器可以独立地具有基于它们的ACF有条件地操作的不同单元。

70. 发明授权

US06622234B1 Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions 有权
标题翻译：用于启动和重新同步多周期SIMD指令的方法和装置
公开(公告)号：US06622234B1
公开(公告)日：2003-09-16
申请号：US09598564
申请日：2000-06-21
申请人： Gerald G. Pechanek , David Carl Strube , Edward A. Wolff , Edwin Frank Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
发明人： Gerald G. Pechanek , David Carl Strube , Edward A. Wolff , Edwin Frank Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30149 , G06F9/325 , G06F9/3836 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3887
摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data, stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.
摘要翻译：描述了使用单个指令多个数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂的指令及其伴随的多周期执行单元的技术。在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作。还描述了许多有利的浮点指令。

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