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1. 发明授权

US08724006B2 Focal plane coding for digital imaging 有权
标题翻译：焦平面编码用于数字成像
公开(公告)号：US08724006B2
公开(公告)日：2014-05-13
申请号：US10784472
申请日：2004-02-24
申请人： David Brady , Michael D Feldman , Nikos P. Pitsianis
发明人： David Brady , Michael D Feldman , Nikos P. Pitsianis
IPC分类号： H04N5/225
CPC分类号： H04N5/2254 , H04N5/349
摘要： An imaging system includes an array of lenses, a plurality of sensor pixels for each lens, the sensor pixels being on an image plane of the imaging system, and a corresponding plurality of focal plane coding elements. A focal plane coding element for each sensor pixel has multiple sub-pixel resolution elements. The focal plane coding element being between the lens and each sensor pixel, wherein sub-pixel resolution elements over the plurality of focal plane coding elements represent a selected transform matrix having a non-zero determinant. The output of the plurality of sensor pixels being an image multiplied by this matrix.
摘要翻译：成像系统包括透镜阵列，用于每个透镜的多个传感器像素，所述传感器像素位于所述成像系统的图像平面上，以及对应的多个焦平面编码元件。每个传感器像素的焦平面编码元件具有多个子像素分辨率元素。焦平面编码元件在透镜和每个传感器像素之间，其中多个焦平面编码元件上的子像素分辨率元素表示具有非零行列式的所选择的变换矩阵。多个传感器像素的输出是乘以该矩阵的图像。

2. 发明申请

US20120124335A1 System Core for Transferring Data Between an External Device and Memory 有权
标题翻译：用于在外部设备和内存之间传输数据的系统核心
公开(公告)号：US20120124335A1
公开(公告)日：2012-05-17
申请号：US13344339
申请日：2012-01-05
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Franklin Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Franklin Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F9/312
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

3. 发明授权

US08082372B2 Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller 有权
公开(公告)号：US08082372B2
公开(公告)日：2011-12-20
申请号：US13113412
申请日：2011-05-23
申请人： Edwin Franklin Barry , Nikos P. Pitsianis , Kevin Coopman
发明人： Edwin Franklin Barry , Nikos P. Pitsianis , Kevin Coopman
IPC分类号： G06F15/80 , G06F13/00
CPC分类号： G06F13/28
摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.

4. 发明授权

US07962719B2 Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture 有权
标题翻译：在ManArray架构上实现高效的复数乘法和快速傅立叶变换（FFT）实现
公开(公告)号：US07962719B2
公开(公告)日：2011-06-14
申请号：US12187746
申请日：2008-08-07
申请人： Nikos P. Pitsianis , Gerald George Pechanek , Ricardo Rodriguez
发明人： Nikos P. Pitsianis , Gerald George Pechanek , Ricardo Rodriguez
IPC分类号： G06F15/76 , G06F9/302
CPC分类号： G06F15/82 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3853 , G06F9/3885 , G06F15/8023 , G06F15/8038 , G06F17/142
摘要： Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.
摘要翻译：提供了复数乘法结果和非常有效的快速傅里叶变换（FFT）的有效计算。采用并行阵列VLIW数字信号处理器以及与计算重叠的处理元件之间的专用复数乘法指令和通信操作，以提供非常高的性能操作。使用紧密封装的VLIW的循环的连续迭代，允许有效地使用复数乘法管线硬件。此外，描述了用于支持组合乘法累加操作的有效技术。

5. 发明授权

US07962667B2 System core for transferring data between an external device and memory 有权
标题翻译：用于在外部设备和存储器之间传输数据的系统核心
公开(公告)号：US07962667B2
公开(公告)日：2011-06-14
申请号：US11827548
申请日：2007-07-12
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

6. 发明授权

US06795909B2 Methods and apparatus for ManArray PE-PE switch control 有权
标题翻译： ManArray PE-PE开关控制的方法和装置
公开(公告)号：US06795909B2
公开(公告)日：2004-09-21
申请号：US10114646
申请日：2002-04-01
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F1517
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
摘要翻译：使用接收模型描述处理元件切换连接控制的处理元件，该接收模型排除在同步MIMD操作模式中发生通信危险。这样的控制允许利用诸如歧管阵列处理架构的架构有效地实现不同的通信拓扑和各种处理效果，例如阵列转置，超补充等。编码指令方法通过利用大多数算法仅使用所有可能的多路复用器设置的一小部分的识别来减少程序员的状态信息和设置负担的量。因此，通过基于由PE通信指令指定的通信路径变换PE标识，可以使用有效的开关控制机构。该控制机制允许PE寄存器广播操作以及相同互连网络上的标准网格和超立方体通信路径。 PE到PE通信指令PEXCHG，SPRECV和SPSEND也被定义和实现。

7. 发明授权

US6167502A Method and apparatus for manifold array processing 失效
标题翻译：用于歧管阵列处理的方法和装置
公开(公告)号：US6167502A
公开(公告)日：2000-12-26
申请号：US949122
申请日：1997-10-10
申请人： Gerald G. Pechanek , Nikos P. Pitsianis , Edwin F. Barry , Thomas L. Drabenstott
发明人： Gerald G. Pechanek , Nikos P. Pitsianis , Edwin F. Barry , Thomas L. Drabenstott
IPC分类号： G06F15/80 , G06F15/00
CPC分类号： G06F15/8023
摘要： A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
摘要翻译：歧管阵列拓扑包括以簇排列的处理元件，节点，存储器等。集群通过集群交换机布置连接，其有利地允许组织的改变而不需要处理元件的物理重排。也实现了预先存在的阵列的典型互连数量的显着减少。快速，高效和经济高效的处理和通信带来了可扩展性的附加优势。

8. 发明申请

US20120331185A1 Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller 失效
标题翻译：使用DMA控制器提供位反转和组播功能的方法和装置
公开(公告)号：US20120331185A1
公开(公告)日：2012-12-27
申请号：US13545067
申请日：2012-07-10
申请人： Edwin F. Barry , Nikos P. Pitsianis , Kevin Coopman
发明人： Edwin F. Barry , Nikos P. Pitsianis , Kevin Coopman
IPC分类号： G06F15/80
CPC分类号： G06F13/28
摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
摘要翻译：描述了用于向多个存储器提供改进的数据分配和从多个存储器收集的技术。这种存储器通常与阵列处理器内的处理元件（PE）相关联并且位于本地。数据处理系统中的改进的数据传输控制通过在数字信号处理器（DSP）上与FFT计算并行执行的多个PE上的数据重排序或位反转寻址来提供基数2,4和8快速傅里叶变换（FFT）算法的支持）数组。还支持通过组播和数据包采集操作的并行数据分发和收集。

9. 发明申请

US20100257290A1 Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller 有权
标题翻译：使用DMA控制器提供位反转和组播功能的方法和装置
公开(公告)号：US20100257290A1
公开(公告)日：2010-10-07
申请号：US12819302
申请日：2010-06-21
申请人： Edwin F. Barry , Nikos P. Pitsianis , Kevin Coopman
发明人： Edwin F. Barry , Nikos P. Pitsianis , Kevin Coopman
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
摘要翻译：描述了用于向多个存储器提供改进的数据分配和从多个存储器收集的技术。这种存储器通常与阵列处理器内的处理元件（PE）相关联并且位于本地。数据处理系统中的改进的数据传输控制通过在数字信号处理器（DSP）上与FFT计算并行执行的多个PE上的数据重排序或位反转寻址来提供基数2,4和8快速傅里叶变换（FFT）算法的支持）数组。还支持通过组播和数据包采集操作的并行数据分发和收集。

10. 发明授权

US07266620B1 System core for transferring data between an external device and memory 有权
标题翻译：用于在外部设备和存储器之间传输数据的系统核心
公开(公告)号：US07266620B1
公开(公告)日：2007-09-04
申请号：US10797726
申请日：2004-03-10
申请人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： A system core having an internal memory which transfers data from an external device to the internal memory is described. To this end, the system core includes a processor, a direct memory access (DMA) controller, an instruction memory and a plurality of memories. The instruction memory contains processor instructions and DMA instructions. The DMA controller fetches DMA instructions from the instruction memory. The DMA controller executes the fetched DMA instructions and thus populates the plurality of memories with data from the external device. The processor then operates on the data found in the populated memories.
摘要翻译：描述具有将数据从外部设备传送到内部存储器的内部存储器的系统核心。为此，系统核心包括处理器，直接存储器访问（DMA）控制器，指令存储器和多个存储器。指令存储器包含处理器指令和DMA指令。 DMA控制器从指令存储器中获取DMA指令。 DMA控制器执行所提取的DMA指令，并且由此来自外部设备的数据填充多个存储器。然后，处理器对在填充的存储器中找到的数据进行操作。

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