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61. 发明申请

US20090292901A1 MICROPROCESSOR APPARATUS AND METHOD FOR PERSISTENT ENABLEMENT OF A SECURE EXECUTION MODE 有权
标题翻译：用于安全执行模式的微处理器装置和方法
公开(公告)号：US20090292901A1
公开(公告)日：2009-11-26
申请号：US12263221
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/318
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The secure application program is executed exclusively within a secure execution mode within the microprocessor. The non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-volatile enabled indicator register that is configured indicate whether the microprocessor is within the secure execution mode or a non-secure execution mode, where contents of the non-volatile enabled indicator register persist through power removal and reapplication to the microprocessor. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：一种提供包括微处理器和安全非易失性存储器的安全执行环境的装置。微处理器执行非安全应用程序和安全应用程序。安全应用程序仅在微处理器内的安全执行模式下执行。通过系统总线从系统存储器访问非安全应用程序。微处理器具有非易失性使能指示符寄存器，其被配置为指示微处理器是处于安全执行模式还是非安全执行模式，其中非易失性使能指示符寄存器的内容通过电力消除持续并重新应用于微处理器。安全非易失性存储器经由专用总线耦合到微处理器，并被配置为存储安全应用程序，其中微处理器和安全非易失性存储器之间的专用总线上的事务与系统总线和对应的系统隔离微处理器内的总线资源。

62. 发明授权

US07380109B2 Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor 有权
标题翻译：在微处理器的现有指令集中提供扩展地址模式的装置和方法
公开(公告)号：US07380109B2
公开(公告)日：2008-05-27
申请号：US10227571
申请日：2002-08-22
申请人： G. Glenn Henry , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/44
CPC分类号： G06F9/30185 , G06F9/30189 , G06F9/342
摘要： An apparatus and method are provided for extending a microprocessor instruction set to allow for extended size addresses. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into an associated micro instruction sequence for execution by the microprocessor, where the extended instruction has an extended prefix and an extended prefix tag. Extended prefix specifies an extended address mode for an address calculation corresponding to an operation, where the extended address mode not otherwise provided for by instructions in an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the associated micro instruction sequence, and performs the address calculation to generate an extended address according to the extended address mode.
摘要翻译：提供了一种用于扩展微处理器指令集以允许扩展大小地址的装置和方法。该装置包括翻译逻辑和扩展执行逻辑。翻译逻辑将扩展指令转换成相关联的微指令序列以供微处理器执行，其中扩展指令具有扩展前缀和扩展前缀标签。扩展前缀指定对应于操作的地址计算的扩展地址模式，其中扩展地址模式不是由现有指令集中的指令另外提供的。扩展前缀标记指示扩展前缀，其中扩展前缀标记是现有指令集中另外以结构体系指定的操作码。扩展执行逻辑耦合到转换逻辑。扩展执行逻辑接收相关联的微指令序列，并且根据扩展地址模式执行地址计算以生成扩展地址。

63. 发明授权

US06928537B2 Split history tables for branch prediction 有权
标题翻译：拆分分支预测的历史表
公开(公告)号：US06928537B2
公开(公告)日：2005-08-09
申请号：US10195083
申请日：2002-07-12
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3806 , G06F9/3844
摘要： An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a first table, a second table, and selection logic. The first table stores branch histories for a first set of branch instructions where the first set, when executed, exhibits a bias toward a first outcome. The second table stores second branch histories for a second set of branch instructions, where, the second set, when executed, exhibits a bias toward a second outcome. The selection logic is coupled to the first and second tables. The selection logic selects a particular branch history from either of the first or second tables. Thus, a branch prediction is made based upon contents of a branch history that is selected from a table containing branch histories for other branch instructions that exhibit the same outcome tendency as the particular branch instruction, thereby reducing the negative effects of aliasing.
摘要翻译：提供了一种装置和方法，用于在流水线微处理器执行之前准确预测分支指令的结果。该装置包括第一表，第二表和选择逻辑。第一表存储用于第一组分支指令的分支历史，其中第一组在执行时表现出朝向第一结果的偏见。第二表存储第二组分支指令的第二分支历史，其中第二组在执行时表现出朝向第二结果的偏向。选择逻辑耦合到第一和第二表。选择逻辑从第一或第二表中的任何一个中选择特定分支历史。因此，基于从包含与特定分支指令相同的结果趋势的其他分支指令的分支历史的表中选择的分支历史的内容进行分支预测，从而减少混叠的负面影响。

64. 发明授权

US06571331B2 Static branch prediction mechanism for conditional branch instructions 有权
标题翻译：条件分支指令的静态分支预测机制
公开(公告)号：US06571331B2
公开(公告)日：2003-05-27
申请号：US09825435
申请日：2001-04-03
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F932
CPC分类号： G06F9/3846 , G06F9/3848
摘要： An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus has a static branch predictor, a mandatory signal, and a biased prediction correlator. The static branch predictor provides a predicted outcome for a branch instruction, and determines if the branch instruction is a biased outcome conditional branch instruction. The mandatory signal is coupled to the static branch predictor and indicates whether or not the branch instruction is the biased outcome conditional branch instruction, thereby indicating whether or not the predicted outcome takes precedence over a dynamic branch prediction for the branch instruction. The biased prediction correlator is coupled to the static branch predictor and the mandatory signal. The biased prediction correlator receives the predicted outcome, the mandatory signal, and the dynamic branch prediction. The biased prediction correlator favors the dynamic branch prediction over the predicted outcome. If the mandatory signal indicates that the branch instruction is a biased outcome conditional branch instruction, however, then the biased prediction correlator favors the predicted outcome over the dynamic branch prediction.
摘要翻译：提供了一种装置和方法，用于在流水线微处理器执行之前准确预测分支指令的结果。该装置具有静态分支预测器，强制信号和偏置预测相关器。静态分支预测器提供分支指令的预测结果，并确定分支指令是否是有偏转的结果条件分支指令。强制信号耦合到静态分支预测器，并指示分支指令是否是有偏转的结果条件分支指令，从而指示预测结果是否优先于分支指令的动态分支预测。偏置预测相关器耦合到静态分支预测器和强制信号。偏置预测相关器接收预测结果，强制信号和动态分支预测。偏好预测相关器有利于预测结果的动态分支预测。然而，如果强制信号指示分支指令是有偏转的结果条件分支指令，则偏置预测相关器有利于动态分支预测的预测结果。

65. 发明授权

US06421774B1 Static branch predictor using opcode of instruction preceding conditional branch 有权
标题翻译：静态分支预测器使用条件分支前面的指令操作码
公开(公告)号：US06421774B1
公开(公告)日：2002-07-16
申请号：US09434090
申请日：1999-11-05
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F932
CPC分类号： G06F9/3846 , G06F9/3848
摘要： An improved Agree branch predictor is provided. The branch predictor biasing bit is generated by a static predictor that makes a static prediction. The static predictor maintains a register storing an instruction preceding a conditional branch instruction for which the prediction is to be made. The static predictor makes the static prediction based upon a table of predetermined combinations of the preceding instruction type and upon a test type specifying a condition upon which the conditional branch instruction will be taken. In addition, the static predictor makes the static prediction based upon the sign of a displacement for calculating a target address of the branch. The static prediction is correlated with an Agree/Disagree prediction generated by a history table of previous outcomes of conditional branch instructions.
摘要翻译：提供了一个改进的同意分支预测器。分支预测器偏置位由静态预测器产生，该静态预测器进行静态预测。静态预测器维持一个寄存器，该寄存器存储一个条件分支指令之前的指令，该指令将进行预测。静态预测器基于前述指令类型的预定组合的表格以及指定将采用条件分支指令的条件的测试类型进行静态预测。另外，静态预测器基于用于计算分支的目标地址的位移的符号进行静态预测。静态预测与由条件分支指令的先前结果的历史表生成的同意/不同意预测相关。

66. 发明授权

US6134573A Apparatus and method for absolute floating point register addressing 失效
标题翻译：绝对浮点寄存器寻址的装置和方法
公开(公告)号：US6134573A
公开(公告)日：2000-10-17
申请号：US63282
申请日：1998-04-20
申请人： G. Glenn Henry , Albert J. Loper, Jr. , Terry Parks
发明人： G. Glenn Henry , Albert J. Loper, Jr. , Terry Parks
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3017 , G06F9/30134 , G06F9/30163 , G06F9/30167 , G06F9/384 , G06F9/3863
摘要： An apparatus and method for improving the execution of floating point instructions in a microprocessor is provided. During decode of a floating point instruction, translation logic generates absolute addresses of specified registers in a floating point register file. These absolute references, as opposed to relative references to a top-of-stack, are inserted into associated micro instructions. In the event of an exception, synchronization logic provides an architected top-of-stack for the floating point instruction associated with the exception to the translation logic so that subsequent instructions will properly reference floating point registers.
摘要翻译：提供了一种用于改善微处理器中浮点指令执行的装置和方法。在解码浮点指令期间，转换逻辑在浮点寄存器文件中生成指定寄存器的绝对地址。这些绝对引用，而不是相对于顶层堆栈的引用，被插入到相关的微指令中。在发生异常的情况下，同步逻辑为与转换逻辑的异常相关联的浮点指令提供了架构化的堆栈顶点，以便后续指令将适当地引用浮点寄存器。

67. 发明授权

US6014743A Apparatus and method for recording a floating point error pointer in zero cycles 失效
标题翻译：用于在零周期中记录浮点误差指针的装置和方法
公开(公告)号：US6014743A
公开(公告)日：2000-01-11
申请号：US19452
申请日：1998-02-05
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/22 , G06F9/302 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/226 , G06F9/3861
摘要： An apparatus and method for recording a floating point macro instruction error pointer within a microprocessor is provided. The apparatus includes translation/control logic for generating a micro instruction sequence to perform a floating point operation. The micro instruction sequence includes a first micro instruction, inserted in the sequence in place of a translate slip, which directs the microprocessor to store a first part of the floating point macro instruction error pointer associated with a floating point macro instruction. The micro instruction sequence also includes a micro instruction extension, associated with a floating point micro instruction within the sequence. The extension directs the microprocessor to store a second part of the floating point macro instruction error pointer. The error pointer is stored in zero effective time increments without requiring additional hardware.
摘要翻译：提供了一种用于在微处理器内记录浮点宏指令错误指针的装置和方法。该装置包括用于产生微指令序列以执行浮点运算的转换/控制逻辑。微指令序列包括以该顺序插入代替转印单的第一微指令，其指示微处理器存储与浮点宏指令相关联的浮点宏指令错误指针的第一部分。微指令序列还包括与序列内的浮点微指令相关联的微指令扩展。扩展引导微处理器存储浮点宏指令错误指针的第二部分。错误指针以零有效时间增量存储，无需额外的硬件。

68. 发明授权

US09378019B2 Conditional load instructions in an out-of-order execution microprocessor 有权
标题翻译：无序执行微处理器中的条件加载指令
公开(公告)号：US09378019B2
公开(公告)日：2016-06-28
申请号：US14007077
申请日：2012-04-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30174 , G06F9/30189
摘要： A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.
摘要翻译：微处理器指令转换器将条件加载指令转换成至少两个微指令。无序执行管线执行微指令。为了执行第一微指令，执行单元从寄存器堆的源寄存器接收源操作数，并使用源操作数响应地生成第一结果。为了执行微指令，执行单元接收目的地寄存器的先前值和第一结果，并响应于从第一结果指定的存储器位置读取数据，并且如果满足条件则提供作为数据的第二结果，这是以前的目标寄存器值，如果没有。目的地寄存器的先前值包括通过执行作为目的地寄存器相对于第二微指令的最新的有序先前的写入器的微指令而产生的结果。

69. 发明授权

US08910276B2 Apparatus and method for precluding execution of certain instructions in a secure execution mode microprocessor 有权
标题翻译：用于排除在安全执行模式微处理器中执行某些指令的装置和方法
公开(公告)号：US08910276B2
公开(公告)日：2014-12-09
申请号：US12263263
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F21/00 , G06F21/72 , G06F21/70
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure execution mode logic that is configured to monitor instructions within the secure application program, and that is configured to preclude execution of certain instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：提供了一种提供安全执行环境的设备。该装置包括微处理器和安全的非易失性存储器。微处理器被配置为执行非安全应用程序和安全应用程序，其中通过系统总线从系统存储器访问非安全应用程序，并且其中以安全执行模式执行安全应用程序。微处理器具有安全执行模式逻辑，其被配置为监视安全应用程序内的指令，并且被配置为排除某些指令的执行。安全非易失性存储器经由专用总线耦合到微处理器，并且被配置为存储安全应用程序，其中微处理器和安全非易失性存储器之间的专用总线上的事务与系统总线隔离，并且对应于微处理器内的系统总线资源。

70. 发明授权

US08856496B2 Microprocessor that fuses load-alu-store and JCC macroinstructions 有权
标题翻译：微处理器融合了load-alu-store和JCC宏指令
公开(公告)号：US08856496B2
公开(公告)日：2014-10-07
申请号：US13034808
申请日：2011-02-25
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30007 , G06F9/3004 , G06F9/30145 , G06F9/3017 , G06F9/3857 , G06F9/3861
摘要： A microprocessor receives first and second program-adjacent macroinstructions of the microprocessor instruction set architecture. The first macroinstruction loads an operand from a location in memory, performs an arithmetic/logic operation using the loaded operand to generate a result, and stores the result back to the memory location. The second macroinstruction jumps to a target address if condition codes satisfy a specified condition and otherwise executes the next sequential instruction. An instruction translator simultaneously translates the first and second program-adjacent macroinstructions into first, second, and third micro-operations for execution by execution units. The first micro-operation calculates the memory location address and loads the operand therefrom. The second micro-operation performs the arithmetic/logic operation using the loaded operand to generate the result, updates the condition codes based on the result, and jumps to the target address if the updated condition codes satisfy the condition. The third micro-operation stores the result to the memory location.
摘要翻译：微处理器接收微处理器指令集架构的第一和第二程序相邻宏指令。第一宏指令从存储器中的位置加载操作数，使用加载的操作数执行算术/逻辑运算以生成结果，并将结果存储回存储器位置。如果条件代码满足指定条件，则第二个宏指令跳转到目标地址，否则执行下一个顺序指令。指令翻译器同时将第一和第二程序相邻的宏指令转换为执行单元执行的第一，第二和第三微操作。第一个微操作计算存储器位置地址并从中加载操作数。第二微操作使用加载的操作数执行算术/逻辑运算，以生成结果，根据结果更新条件代码，如果更新的条件代码满足条件，则跳转到目标地址。第三个微操作将结果存储到内存位置。

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