专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20110051519A1 Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 审中-公开
标题翻译：新型基于NAND的混合NVM设计，将NAND和NOR集成在1-die与串行接口中
公开(公告)号：US20110051519A1
公开(公告)日：2011-03-03
申请号：US12807080
申请日：2010-08-27
申请人： Peter W. Lee , Kesheng Wang , Fu-Chang Hsu
发明人： Peter W. Lee , Kesheng Wang , Fu-Chang Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/32 , G11C7/1075
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. An enable signal defines a beginning and termination of a reading or writing operation. Reading one nonvolatile memory array may be interrupted for another operation and then resumed.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在串行接口上传输。串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码启用信号定义读取或写入操作的开始和结束。读取一个非易失性存储器阵列可能被中断用于另一个操作，然后恢复。

62. 发明授权

US08775719B2 NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface 失效
标题翻译：基于NAND的混合NVM设计，在单模并行接口中集成NAND和NOR
公开(公告)号：US08775719B2
公开(公告)日：2014-07-08
申请号：US12807996
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1075 , G11C2216/22
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在并行接口上传输。并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

63. 发明申请

US20110072200A1 Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface 失效
标题翻译：新型基于NAND的混合NVM设计，将NAND和NOR集成在1模并行接口中
公开(公告)号：US20110072200A1
公开(公告)日：2011-03-24
申请号：US12807996
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/02 , G11C16/06
CPC分类号： G11C16/10 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1075 , G11C2216/22
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在并行接口上传输。并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

64. 发明申请

US20110051524A1 Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device 失效
标题翻译：用于操作NAND类双电荷保持晶体管NOR闪存器件的方法和装置
公开(公告)号：US20110051524A1
公开(公告)日：2011-03-03
申请号：US12806848
申请日：2010-08-23
申请人： Fu-Chang Hsu , Peter W. Lee
发明人： Fu-Chang Hsu , Peter W. Lee
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0458 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C16/3477 , G11C2211/5621
摘要： A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state.
摘要翻译：用于NAND类型的双电荷保持晶体管NOR闪存单元的操作的方法和装置开始于擦除，验证将擦除的电荷保持晶体管的阈值电压电平擦除为已擦除的阈值电压电平。然后，通过将NAND类双电荷保持晶体管NOR闪存单元的两个电荷保持晶体管中的一个编程为第一编程阈值电压电平，并编程NAND类似的双电荷保持的两个电荷保持晶体管中的另一个来进行方法晶体管NOR闪存单元到第一编程阈值电压电平或第二编程阈值电压电平。擦除阈值电压电平和第一和第二编程阈值电压电平的组合确定NAND类似的双电荷保持晶体管NOR闪存单元的内部数据状态，然后对其进行解码以确定外部数据逻辑状态。

65. 发明授权

US08355287B2 Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device 失效
标题翻译：用于操作NAND类双电荷保持晶体管NOR闪存器件的方法和装置
公开(公告)号：US08355287B2
公开(公告)日：2013-01-15
申请号：US12806848
申请日：2010-08-23
申请人： Fu-Chang Hsu , Peter W. Lee
发明人： Fu-Chang Hsu , Peter W. Lee
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0458 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C16/3477 , G11C2211/5621
摘要： A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state.
摘要翻译：用于NAND类型的双电荷保持晶体管NOR闪存单元的操作的方法和装置开始于擦除，验证将擦除的电荷保持晶体管的阈值电压电平擦除为已擦除的阈值电压电平。然后，通过将NAND类双电荷保持晶体管NOR闪存单元的两个电荷保持晶体管中的一个编程为第一编程阈值电压电平，并编程NAND类似的双电荷保持的两个电荷保持晶体管中的另一个来进行方法晶体管NOR闪存单元到第一编程阈值电压电平或第二编程阈值电压电平。擦除阈值电压电平和第一和第二编程阈值电压电平的组合确定NAND类似的双电荷保持晶体管NOR闪存单元的内部数据状态，然后对其进行解码以确定外部数据逻辑状态。

66. 发明授权

US06374770B1 Apparatus for improving film stability of halogen-doped silicon oxide films 失效
标题翻译：用于提高卤素掺杂氧化硅膜的膜稳定性的装置
公开(公告)号：US06374770B1
公开(公告)日：2002-04-23
申请号：US09597856
申请日：2000-06-20
申请人： Peter W. Lee , Stuardo Robles , Anand Gupta , Virendra V. S. Rana , Amrita Verma
发明人： Peter W. Lee , Stuardo Robles , Anand Gupta , Virendra V. S. Rana , Amrita Verma
IPC分类号： C23C1600
CPC分类号： H01L21/02131 , C23C16/401 , C23C16/56 , H01L21/02274 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31629
摘要： A chemical vapor deposition system that includes a housing configured to form a processing chamber, a substrate holder configured to hold a substrate within the processing chamber, a gas distribution system configured to introduce gases into the processing chamber, a plasma generation system configured to form a plasma within the processing chamber, a processor operatively coupled to control the gas distribution system and the plasma generation system, and a computer-readable memory coupled to the processor that stores a computer-readable program which directs the operation of the chemical vapor deposition system. In one embodiment the computer-readable program comprises instructions that control the gas distribution system to flow a process gas comprising silicon, oxygen and a halogen family member into the chamber to deposit a halogen-doped silicon oxide film on a substrate positioned on the substrate holder and instructions that control the gas distribution system and plasma generation system to densify the halogen-doped silicon oxide film by bombarding the film with ionic species from a plasma of an argon-containing gas source. In another embodiment, the computer-readable program comprises instructions that control the gas distribution system to flow a process gas comprising silicon, oxygen and a halogen family member into the chamber to deposit a halogen-doped silicon oxide film on said substrate and instructions that control the gas distribution system and plasma generation system to form a plasma from a hydrogen containing source gas to bombard the halogen-doped silicon oxide film with hydrogen ions to remove loosely bound halogen atoms from the film.
摘要翻译：一种化学气相沉积系统，其包括构造成形成处理室的壳体，被配置为在处理室内保持衬底的衬底保持器，配置成将气体引入到处理室中的气体分配系统;等离子体生成系统，处理室内的等离子体，可操作地耦合以控制气体分配系统和等离子体生成系统的处理器以及耦合到处理器的计算机可读存储器，其存储引导化学气相沉积系统的操作的计算机可读程序。在一个实施例中，计算机可读程序包括控制气体分配系统以将包含硅，氧和卤素族成员的工艺气体流入室中的指令，以将沉积卤素掺杂的氧化硅膜沉积在位于衬底保持器以及控制气体分配系统和等离子体发生系统通过用来自含氩气体源的等离子体的离子物质轰击膜来致密化掺杂氧化硅膜的指令。在另一个实施例中，计算机可读程序包括控制气体分配系统以使包含硅，氧和卤素族成员的工艺气体流入腔室中以在所述衬底上沉积卤素掺杂的氧化硅膜的指令，以及控制气体分配系统和等离子体发生系统，以形成来自含氢源气体的等离子体，用氢离子轰击卤素掺杂的氧化硅膜，以从薄膜中去除松散结合的卤素原子。

67. 发明授权

US5600586A Flat-cell ROM and decoder 失效
标题翻译：平板ROM和解码器
公开(公告)号：US5600586A
公开(公告)日：1997-02-04
申请号：US279682
申请日：1994-07-25
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： H01L27/112 , G11C17/12 , H01L21/8246 , G11C17/00
CPC分类号： G11C17/126
摘要： A flat-cell ROM array includes a bank of field effect transistors, each having a source, drain and gate, formed by ion implantation between columns of buried N+ and under rows of polysilicon, wherein adjacent columns of buried N+ are the source and drain of at least one transistor and a corresponding row of polysilicon is the gate of the transistor. Each of these transistors is programmed to have one of a plurality of threshold voltages depending on a desired storage value. Attached to the bank of transistors is an upper selector network associated with the bank connected to a first class of alternating sets of the columns, and a lower selector network associated with the bank connected to a second class of alternating sets of the columns. A method provides steps for performing the present invention.
摘要翻译：平面单元ROM阵列包括一组场效应晶体管，每一个具有源极，漏极和栅极，通过离子注入在掩埋N +的列之间和下行多晶硅之间形成，其中相邻的掩埋N +列是源极和漏极至少一个晶体管和对应的多晶硅行是晶体管的栅极。根据期望的存储值，将这些晶体管中的每一个编程为具有多个阈值电压中的一个。连接到晶体管组的是与连接到第一类交替列列的存储体相关联的上选择器网络，以及与连接到第二类交替列列的存储体相关联的下选择器网络。一种方法提供了执行本发明的步骤。

68. 发明授权

US4601592A Tapered roller bearing capable of sustained operation without lubricant replenishment 失效
标题翻译：圆锥滚子轴承能够持续运行，无需润滑剂补充
公开(公告)号：US4601592A
公开(公告)日：1986-07-22
申请号：US578025
申请日：1984-02-08
申请人： Chester F. Jatczak , Peter W. Lee , Peter S. Orvos
发明人： Chester F. Jatczak , Peter W. Lee , Peter S. Orvos
IPC分类号： F16C19/36 , F16C19/52 , F16C33/60 , F16C33/66 , F16C33/58 , F16C33/36
CPC分类号： F16C33/605 , F16C19/364 , F16C33/4605 , F16C33/543 , F16C33/6648 , Y10S384/902
摘要： A tapered roller bearing has a porous rib ring against which the large ends of its wrought steel tapered rollers bear so that the ring prevents the rollers from being expelled. The rib ring is formed from porous powdered steel that has been compacted to a density of about 70% to 85% of theoretical and then sintered and machined. Thereafter, the machined rib ring is etched to expose the pores at the surface against which the large ends of the rollers bear. Finally, the rib ring is impregnated with oil. Should the bearing lose its normal supply of lubrication, the critical region of contact between the abutment face on the rib ring and the large ends of the rollers will nevertheless be adequately lubricated for a reasonable time by lubricant which escapes from the pores of the rib ring. The cage of the bearing may be piloted by the rib ring and by a ring-like cup insert that is formed in the same manner as the rib ring.
摘要翻译：圆锥滚子轴承具有多孔肋环，其锻造圆锥滚子的大端承受着多个肋环，使得环防止辊被排出。肋环由多孔粉末状钢制成，其已被压实成理论值的约70％至85％的密度，然后烧结和加工。此后，对机加工的肋环进行蚀刻以暴露出辊的大端承载的表面的孔。最后，肋环用油浸渍。如果轴承失去正常的润滑润滑，则肋环上的邻接面与辊的大端之间的临界接触区域在合理的时间内将通过从肋环孔隙逸出的润滑剂充分润滑。轴承的保持架可以由肋环和与肋环相同的方式形成的环状杯形插入件引导。

69. 发明授权

US07369438B2 Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications 有权
标题翻译：多功能java卡，SIM卡，生物护照和生物识别卡应用的组合内存设计和技术
公开(公告)号：US07369438B2
公开(公告)日：2008-05-06
申请号：US11305700
申请日：2005-12-16
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： G11C11/34
CPC分类号： G11C11/005 , G11C16/0408 , G11C16/0483 , G11C17/12 , H01L27/115 , H01L29/0646 , H01L29/7885
摘要： A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that each array may be addressed with common addressing signals. The combination volatile and nonvolatile memory integrated circuit further has a memory control circuit in communication with external circuitry to receive address, command, and data signals. The memory control circuit interprets the address, command, and data signals, and for transfer to the volatile memory array and the nonvolatile memory arrays for reading, writing, programming, and erasing the volatile and nonvolatile memory arrays. The volatile memory array is may be a SRAM, a pseudo SRAM, or a DRAM. Any of the nonvolatile memory arrays maybe masked programmed ROM arrays, NAND configured flash memory NAND configured EEPROM.
摘要翻译：易失性和非易失性存储器集成电路的组合具有放置在基板和多个非易失性存储器阵列上的至少一个易失性存储器阵列。易失性和非易失性存储器阵列具有彼此相关联的地址空间，使得每个阵列可以用公共寻址信号寻址。组合易失性和非易失性存储器集成电路还具有与外部电路通信的存储器控制电路，以接收地址，命令和数据信号。存储器控制电路解释地址，命令和数据信号，并且用于传送到易失性存储器阵列和用于读取，写入，编程和擦除易失性和非易失性存储器阵列的非易失性存储器阵列。易失性存储器阵列可以是SRAM，伪SRAM或DRAM。任何非易失性存储器阵列都可以屏蔽编程的ROM阵列，NAND配置闪存NAND配置的EEPROM。

70. 发明授权

US06891221B2 Array architecture and process flow of nonvolatile memory devices for mass storage applications 有权
标题翻译：用于大容量存储应用的非易失性存储器件的阵列架构和处理流程
公开(公告)号：US06891221B2
公开(公告)日：2005-05-10
申请号：US10790578
申请日：2004-03-01
申请人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
发明人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0491 , H01L27/115
摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.
摘要翻译：在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。通过使用Fowler-Nordheim从浮置栅极到控制栅极的隧道，通过在浮栅的壁上形成的多晶硅氧化物来消除电池。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式