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61. 发明授权

US07669159B2 IC tiling pattern method, IC so formed and analysis method 有权
标题翻译： IC贴片图案法，IC形成及分析方法
公开(公告)号：US07669159B2
公开(公告)日：2010-02-23
申请号：US11160339
申请日：2005-06-20
申请人： Robert J. Allen , John M. Cohn , Peter A. Habitz , William Leipold , Ivan Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Peter A. Habitz , William Leipold , Ivan Wemple , Paul S. Zuchowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L21/3212 , H01L27/0207
摘要： The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patterns (32, 34) oriented substantially parallel to electrical structure regardless of their angle. A method of electrical analysis based on this provision is also provided as is a related program product.
摘要翻译：本发明提供一种用于提供集成电路（6）的方法，所述集成电路（6）在IC的非正交角的部分（10,12,14和16）之间具有基本均匀的密度。特别地，本发明提供了基本上平行于电气结构定向的填充平铺图案（32,34），而不管其角度如何。还提供了基于该规定的电分析方法，相关程序产品也是如此。

62. 发明授权

US07418689B2 Method of generating wiring routes with matching delay in the presence of process variation 有权
标题翻译：在存在过程变化的情况下生成具有匹配延迟的布线路线的方法
公开(公告)号：US07418689B2
公开(公告)日：2008-08-26
申请号：US10908102
申请日：2005-04-27
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

63. 发明授权

US07289659B2 Method and apparatus for manufacturing diamond shaped chips 有权
标题翻译：用于制造菱形芯片的方法和装置
公开(公告)号：US07289659B2
公开(公告)日：2007-10-30
申请号：US10250295
申请日：2003-06-20
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

64. 发明授权

US06854099B2 Balanced accuracy for extraction 失效
标题翻译：平衡精度提取
公开(公告)号：US06854099B2
公开(公告)日：2005-02-08
申请号：US10064300
申请日：2002-07-01
申请人： Lewis W. Dewey, III , Peter A. Habitz , Thomas G. Mitchell
发明人： Lewis W. Dewey, III , Peter A. Habitz , Thomas G. Mitchell
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method and system for performing parasitic extraction, wherein the method comprises calculating the minimum output impedance for a network-connected component comprising a plurality of ports thereby producing a labeled impedance, estimating the minimum output impedance for every net, comparing the labeled impedance with the estimated impedance, and selecting the net which needs to be extracted based on a ratio of values of the labeled impedance and the estimated impedance. The step of calculating comprises labeling every port with a minimum size of port impedance, a resistance from a port to power, and a minimum capacitance of a port-net inside the network connected component. The step of estimating comprises using a geometry of segments of the net comprising a summation of area and perimeter values of all the segments of the net, or calculating a resistance over a length of a total net versus an average width of the net.
摘要翻译：一种用于执行寄生提取的方法和系统，其中所述方法包括计算包括多个端口的网络连接部件的最小输出阻抗，从而产生标记阻抗，估计每个网络的最小输出阻抗，将标记阻抗与估计阻抗，以及基于标记阻抗值和估计阻抗的比值来选择需要提取的网络。计算步骤包括以端口阻抗的最小尺寸，从端口到电源的电阻以及网络连接组件内的端口网的最小电容来标记每个端口。估计步骤包括使用网的几何形状，其包括网的所有段的面积和周界值的总和，或者计算总网长度相对于网的平均宽度的电阻。

65. 发明授权

US06574782B1 Decoupled capacitance calculator for orthogonal wiring patterns 有权
标题翻译：用于正交布线图案的去耦电容计算器
公开(公告)号：US06574782B1
公开(公告)日：2003-06-03
申请号：US09713422
申请日：2000-11-15
申请人： L. William Dewey, III , Peter A. Habitz , Thomas G. Mitchell
发明人： L. William Dewey, III , Peter A. Habitz , Thomas G. Mitchell
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A structure and method for extracting parasitic capacitance from a multi-layer wiring structure that creates, for each wiring layer in a wiring structure, a wiring density map and measures a plurality of metal segments in a wiring layer to determine an area occupied by the metal segments. The invention calculates an up area capacitance component for each of the metal segments by multiplying the area occupied by the metal segments by a wiring density from the wiring density map of an overlying wiring layer over the metal segments and by a capacitance coefficient of the overlying wiring layer. To calculate the down area capacitance component for each of the metal segments, the invention multiplies the area occupied by the metal segments by a wiring density, from the wiring density map of an underlying wiring layer under the metal segments and by a capacitance coefficient of the underlying wiring layer. The invention combines the up area capacitance component and the down area capacitance component to form a vertical coupling capacitance component for each of the metal segments.
摘要翻译：一种用于从多层布线结构中提取寄生电容的结构和方法，其对布线结构中的每个布线层产生布线密度图，并测量布线层中的多个金属片段，以确定金属占据的面积细分。本发明通过将金属片段占据的面积乘以金属片上覆盖布线层的布线密度图和布线密度乘以覆盖布线的电容系数来计算每个金属片段的面积电容分量层。为了计算每个金属段的下降面积电容分量，本发明根据金属段下面的布线层的布线密度图和金属段的电容系数将金属段所占的面积乘以布线密度底层布线层。本发明结合了上部区域电容分量和向下区域电容分量，以形成每个金属段的垂直耦合电容分量。

66. 发明申请

US20140046466A1 INTEGRATED CIRCUIT PRODUCT YIELD OPTIMIZATION USING THE RESULTS OF PERFORMANCE PATH TESTING 有权
标题翻译：使用性能路径测试结果的集成电路产品线优化
公开(公告)号：US20140046466A1
公开(公告)日：2014-02-13
申请号：US13570285
申请日：2012-08-09
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
IPC分类号： G05B19/18
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译：公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级或模块级）性能路径测试。在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。然后，基于这种相关性，生产线可以重新居中。可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整进一步降低产量损失。

67. 发明授权

US08539429B1 System yield optimization using the results of integrated circuit chip performance path testing 有权
标题翻译：系统产量优化采用集成电路芯片性能路径测试的结果
公开(公告)号：US08539429B1
公开(公告)日：2013-09-17
申请号：US13572954
申请日：2012-08-13
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/31725
摘要： Disclosed are embodiments of a method, system and computer program for optimizing system yield based on the results of post-manufacture integrated circuit (IC) chip performance path testing. In these embodiments, a correlation is made between IC chip performance measurements, which were acquired from IC chips specifically during post-manufacture (i.e., wafer-level or module-level) performance path testing, and system performance measurements, which were acquired from systems that incorporate those IC chips previously subjected to performance path testing. Based on this correlation and a target system performance value, a post-manufacture (i.e., wafer-level or module-level) chip dispositioning rule can be adjusted to optimize system yield (i.e., to ensure that subsequently manufactured systems which incorporate the IC chip meet the target system performance value). Optionally, simulation of such processing can be performed during design of the IC chip for incorporation into the system in order establish the initial chip dispositioning rule in the first place.
摘要翻译：公开了一种基于后制造集成电路（IC）芯片性能路径测试的结果来优化系统产量的方法，系统和计算机程序的实施例。在这些实施例中，在IC芯片特性在后期制造（即晶片级或模块级）性能路径测试中获得的IC芯片性能测量和从系统获取的系统性能测量之间进行相关其中包含先前经过性能路径测试的那些IC芯片。基于这种相关性和目标系统性能值，可以调整后制造（即晶片级或模块级）芯片布置规则以优化系统产量（即，确保随后制造的并入IC芯片的系统满足目标系统的性能价值）。可选地，可以在用于结合到系统中的IC芯片的设计期间执行这种处理的模拟，以便首先建立初始的芯片布置规则。

68. 发明申请

US20130085726A1 INTEGRATED CIRCUIT DESIGN SIMULATION MATRIX INTERPOLATION 有权
标题翻译：集成电路设计仿真矩阵插值
公开(公告)号：US20130085726A1
公开(公告)日：2013-04-04
申请号：US13251517
申请日：2011-10-03
申请人： Peter A. Habitz , Amol A. Joshi
发明人： Peter A. Habitz , Amol A. Joshi
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Methods and systems perform a simulation on an integrated circuit design by applying a first value to a first variable and a second value to a second variable of the simulation to produce a first matrix corner simulation value. The methods and systems repeat the simulation using different values for the first and said second variables to produce a second matrix corner simulation value, a third matrix corner simulation value, and a fourth matrix corner simulation value. The methods and systems create a matrix, and the matrix has the first matrix corner simulation value, the second matrix corner simulation value, the third matrix corner simulation value, and the fourth matrix corner simulation value. The methods and systems interpolate all remaining values within the matrix based upon existing simulation values within the matrix.
摘要翻译：方法和系统通过将第一值应用于第一变量和第二值到模拟的第二变量来对集成电路设计进行仿真以产生第一矩阵角模拟值。方法和系统使用不同的值对第一和第二变量重复模拟，以产生第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。方法和系统创建矩阵，矩阵具有第一矩阵角模拟值，第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。方法和系统基于矩阵内的现有模拟值来内插矩阵内的所有剩余值。

69. 发明申请

US20120124542A1 Method and System for Optimizing a Device With Current Source Models 有权
标题翻译：使用当前源模型优化设备的方法和系统
公开(公告)号：US20120124542A1
公开(公告)日：2012-05-17
申请号：US12944480
申请日：2010-11-11
申请人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/80 , G06F2217/84
摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.
摘要翻译：一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差分支和第二分支横跨不同的过程电压温度值。

70. 发明申请

US20100327892A1 Parallel Array Architecture for Constant Current Electro-Migration Stress Testing 失效
标题翻译：用于恒流电迁移应力测试的并行阵列架构
公开(公告)号：US20100327892A1
公开(公告)日：2010-12-30
申请号：US12492619
申请日：2009-06-26
申请人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.
摘要翻译：提供了一种用于恒流电迁移应力测试的并行阵列架构。并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分电流源逻辑。使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

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