专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US06986090B2 Method for reducing switching activity during a scan operation with limited impact on the test coverage of an integrated circuit 失效
公开(公告)号：US06986090B2
公开(公告)日：2006-01-10
申请号：US10078876
申请日：2002-02-20
申请人： David J. Hathaway , Brion L. Keller
发明人： David J. Hathaway , Brion L. Keller
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318583
摘要： A method for reducing the switching activity during both scan-in and scan-out operations of an integrated circuit with reduced detrimental effect on test pattern effectiveness and test time is described. The method makes use of a sample set of patterns to determine the probabilities of same and opposite relationships between stimulus and result values, and uses these probabilities to determine memory element pair compatibilities. Scan chains are ordered preferentially by connecting adjacently compatible memory elements, and inversions are inserted between selected memory element pairs based on those probabilities. Unspecified stimulus bits are filled in to reduce the switching activity based on the scan chain ordering and inversions.

62. 发明授权

US06751744B1 Method of integrated circuit design checking using progressive individual network analysis 有权
标题翻译：集成电路设计检查方法采用渐进式单独网络分析
公开(公告)号：US06751744B1
公开(公告)日：2004-06-15
申请号：US09475799
申请日：1999-12-30
申请人： Robert J. Allen , John M. Cohn , David J. Hathaway
发明人： Robert J. Allen , John M. Cohn , David J. Hathaway
IPC分类号： G06F112
CPC分类号： G06F17/504 , G06F2217/78
摘要： A method for checking integrated circuit designs comprising the steps of calculating a first performance parameter by analyzing the network's sensitivity to a signal applied to the network; comparing the first performance parameter to one or more rules to determine a first pass condition and writing the value of first performance parameter to a netlist file in response to a pass to the first pass condition; followed by calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing the second performance parameter to the netlist file in response to a pass to said second pass condition or writing an error flag to the netlist file in response to a fail to said second pass condition is disclosed. The method, at each step, decides if a quick to calculate parameter provides sufficient design margin or if a more accurate but longer to calculate parameter is required.
摘要翻译：一种用于检查集成电路设计的方法，包括以下步骤：通过分析网络对施加到网络的信号的灵敏度来计算第一性能参数; 将所述第一性能参数与一个或多个规则进行比较以确定第一通过条件，并响应于所述第一通过条件的传递将所述第一性能参数的值写入网表文件; 随后基于第一网络模型计算第二性能参数，以响应于所述第一通过条件的失败来确定第二通过条件，并响应于所述第二通过条件的通过将所述第二性能参数写入所述网表文件，或公开了响应于所述第二通过条件的失败向网表文件写入错误标志。该方法在每个步骤中决定快速计算参数是否提供足够的设计余量，或者是否需要更准确但更长的计算参数。

63. 发明授权

US06687883B2 System and method for inserting leakage reduction control in logic circuits 有权
标题翻译：用于在逻辑电路中插入泄漏减少控制的系统和方法
公开(公告)号：US06687883B2
公开(公告)日：2004-02-03
申请号：US09750969
申请日：2000-12-28
申请人： John M. Cohn , Alvar A. Dean , David J. Hathaway , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , David J. Hathaway , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F1/3243 , G06F1/3203 , Y02D10/152 , Y02D50/20
摘要： A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.
摘要翻译：一种用于减少逻辑网络的泄漏功率的方法，包括以下步骤：使用（可观察性）不关心信息以识别各个网络的“睡眠状态”; 基于概率分析确定至少一个网络，其中通过在“睡眠状态”的至少一部分期间将网络强制为特定值来减少预期功率消耗; 并将所确定的网络强制为所述“睡眠状态”的确定值确定部分。

64. 发明授权

US07743355B2 Method of achieving timing closure in digital integrated circuits by optimizing individual macros 失效
标题翻译：通过优化单个宏来实现数字集成电路中的时序闭合的方法
公开(公告)号：US07743355B2
公开(公告)日：2010-06-22
申请号：US11942034
申请日：2007-11-19
申请人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
发明人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

65. 发明授权

US07650246B2 Process and apparatus for estimating circuit delay 失效
标题翻译：用于估计电路延迟的过程和装置
公开(公告)号：US07650246B2
公开(公告)日：2010-01-19
申请号：US11162200
申请日：2005-08-31
申请人： Harry J. Beatty, III , David J. Hathaway , Alexander J. Suess
发明人： Harry J. Beatty, III , David J. Hathaway , Alexander J. Suess
IPC分类号： G01R15/00 , G06F19/00
CPC分类号： G01R31/31725
摘要： A method and device for determining a delay of a gate driven by a driving gate with different ground or supply voltages. The method includes determining from the supply and ground voltages for the driven gate and its driving gate an adjusted supply voltage value, and applying the adjusted supply voltage value as a single voltage parameter to a pre-characterized delay model for the driven gate. The device is structured to perform the method.
摘要翻译：一种用于确定由具有不同接地或电源电压的驱动门驱动的栅极的延迟的方法和装置。该方法包括从驱动栅极及其驱动栅极的电源和地电压确定经调整的电源电压值，并将调整的电源电压值作为单个电压参数应用于驱动栅极的预定义延迟模型。该设备的结构是执行该方法。

66. 发明申请

US20080263488A1 METHOD FOR GENERATING A SKEW SCHEDULE FOR A CLOCK DISTRIBUTION NETWORK CONTAINING GATING ELEMENTS 有权
标题翻译：用于生成包含加注元素的时钟分配网络的SKEW时间表的方法
公开(公告)号：US20080263488A1
公开(公告)日：2008-10-23
申请号：US11737289
申请日：2007-04-19
申请人： Revanta Banerji , David J. Hathaway , Alex Rubin , Alexander J. Suess
发明人： Revanta Banerji , David J. Hathaway , Alex Rubin , Alexander J. Suess
IPC分类号： G06F17/50 , H03H11/26
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.
摘要翻译：用于产生时钟分配网络的偏斜调度的方法产生考虑时钟分配网络的端点处的存储器元件的定时要求以及提供时钟门和其它时钟控制的门控信号的定时要求的调度时钟分配网络中的元素。该方法通过两阶段迭代过程为偏斜调度问题提供了一个完整的解决方案。该过程的两个阶段交替地跟踪通过首先考虑时钟分配网络的门控元件产生的调度，然后平衡可能存在于相同时钟分配网络的存储器元件上的任何剩余的偏移。最后，该方法描述了用于后处理偏斜调度以确保可以使用时钟树生成工具来实现的过程。

67. 发明申请

US20080250279A1 Method of Increasing Path Coverage in Transition Test Generation 失效
标题翻译：在过渡测试生成中增加路径覆盖的方法
公开(公告)号：US20080250279A1
公开(公告)日：2008-10-09
申请号：US11696981
申请日：2007-04-05
申请人： Gary D. Grise , David J. Hathaway , Vikram Iyengar
发明人： Gary D. Grise , David J. Hathaway , Vikram Iyengar
IPC分类号： G01R31/28
CPC分类号： G01R31/31715 , G01R31/31707 , G01R31/318328
摘要： A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.
摘要翻译：一种使用自动测试图案生成工具自动生成数字逻辑电路测试图案的方法。该方法包括生成测试模式并将故障行为应用于数字逻辑电路内的各种路径。随着每个电路路径的测试，沿电路路径的测试电路节点被标记为“行使”。通过避免标记的电路节点组装后续测试路径。以这种方式，可以增加测试路径的覆盖范围，并且可以有效地测试许多电路节点。

68. 发明授权

US07404163B2 Static timing slacks analysis and modification 有权
标题翻译：静态定时松散分析和修改
公开(公告)号：US07404163B2
公开(公告)日：2008-07-22
申请号：US11277385
申请日：2006-03-24
申请人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
发明人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译：公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

69. 发明申请

US20080172638A1 METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLSI) DESIGN BY USE OF CLUSTER-BASED LOGIC CELL CLONING 审中-公开
标题翻译：通过使用基于群集的逻辑单元克隆优化分层级非常大规模集成（VLSI）设计的方法
公开(公告)号：US20080172638A1
公开(公告)日：2008-07-17
申请号：US11623122
申请日：2007-01-15
申请人： Michael S. Gray , David J. Hathaway , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , David J. Hathaway , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of optimizing hierarchical very large scale integration (VLSI) design by use of cluster-based cell cloning. The method of the present invention provides improved yield or migration by reusing cells in order to reduce the number of unique instances of at least one of the reused cells. The method performs hierarchal optimization on the reduced set of clones (i.e., clusters). The method of the present disclosure includes, but is not limited to, the steps of setting the initial clustering parameters; assembling the physical design from existing reused cells; for each cell type, performing a full cloning operation in order to create a full set of duplicate cells; for each cell type, performing a full optimization of the design; for each cell type, performing an analyses of all cell environments and performing a clustering operation; and analyzing the overall results in order to determine whether the optimization objectives are achieved.
摘要翻译：通过使用基于簇的细胞克隆来优化分级超大规模集成（VLSI）设计的方法。本发明的方法通过重新使用细胞来提供改善的产量或迁移，以减少至少一个重复使用的细胞的唯一实例的数量。该方法对减少的克隆集合（即，簇）执行层次优化。本公开的方法包括但不限于设置初始聚类参数的步骤; 从现有的重复使用的电池组装物理设计; 对于每个单元格类型，执行完全克隆操作以便创建一整套重复的单元格; 对于每个单元格类型，执行设计的全面优化; 对于每个单元类型，执行所有单元环境的分析并执行聚类操作; 并分析总体结果，以确定是否实现优化目标。

70. 发明授权

US07280939B2 System and method of analyzing timing effects of spatial distribution in circuits 有权
标题翻译：分析电路中空间分布的时序效应的系统和方法
公开(公告)号：US07280939B2
公开(公告)日：2007-10-09
申请号：US10709362
申请日：2004-04-29
申请人： David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F11/30 , G06F9/45
CPC分类号： G06F17/5031
摘要： Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the size of the bounding region may be used to calculate a timing slack variation factor. The size of the bounding region may be adjusted to account for variability in timing delays. In other embodiments, centroids may be calculated using either the location or the delay-weighted location of elements or cells within the path or cone and the centroids used to calculate timing slack variation factor. The timing slack variation factors are used to calculate a new timing slack for the path or logic cone of the circuit.
摘要翻译：提供了系统和方法，用于通过考虑电路的路径或逻辑锥中的单元或元件的位置来分析电路的定时，包括集成电路。在一个实施例中，可以围绕感兴趣的细胞或元件限定边界区域，并且可以使用边界区域的大小来计算定时松弛变化因子。可以调整边界区域的大小以考虑定时延迟的变化。在其他实施例中，可以使用路径或锥体内的元件或单元的位置或延迟加权位置以及用于计算定时松弛变化因子的质心来计算质心。定时松弛变化因子用于计算电路的路径或逻辑锥的新的定时松弛。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式