专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20070120216A1 LOW COST BONDING PAD AND METHOD OF FABRICATING SAME 有权
标题翻译：低成本接合垫及其制造方法
公开(公告)号：US20070120216A1
公开(公告)日：2007-05-31
申请号：US11164653
申请日：2005-11-30
申请人： Jeffrey Brigante , Zhong-Xiang He , Barbara Waterhouse , Eric White
发明人： Jeffrey Brigante , Zhong-Xiang He , Barbara Waterhouse , Eric White
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/53214 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05554 , H01L2224/05572 , H01L2224/05624 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/16 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48699 , H01L2224/48724 , H01L2224/48799 , H01L2224/48824 , H01L2924/0001 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00
摘要： A structure and a method of forming the structure. The structure including: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene, dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of the last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level; a capping layer in direct physical and electrical contact with a top surface of the last damascene or dual-damascene wire, the last damascene or dual-damascene wire comprising copper; a dielectric passivation layer formed on a top surface of the last interlevel dielectric level; and an aluminum pad in direct physical and electrical contact with the capping layer, a top surface of the aluminum pad not covered by the dielectric passivation layer.
摘要翻译：一种形成结构的结构和方法。该结构包括：集成电路芯片，其具有从第一布线级别到最后布线级别的布线级别的集合，每个布线级别包括嵌入在相应的层间电介质层中的一个或多个镶嵌，双镶嵌线或镶嵌孔，顶部最后一个镶嵌层或最后布线层的双镶嵌线的表面与相应的最后层间介电层的顶表面基本共面; 与最后的镶嵌或双镶嵌线的顶表面直接物理和电接触的封盖层，包括铜的最后镶嵌或双镶嵌线; 形成在最后层间电介质层的顶表面上的电介质钝化层; 以及与覆盖层直接物理和电接触的铝焊盘，铝焊盘的顶表面未被电介质钝化层覆盖。

62. 发明申请

US20070052062A1 VERTICAL LC TANK DEVICE 失效
标题翻译：垂直液相色谱箱装置
公开(公告)号：US20070052062A1
公开(公告)日：2007-03-08
申请号：US11161929
申请日：2005-08-23
申请人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L29/00
CPC分类号： H03L7/099 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L27/0617 , H01L27/0641 , H01L27/08 , H01L27/0811 , H01L28/10 , H01L2924/0002 , H03J3/20 , H01L2924/00
摘要： An LC tank structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.
摘要翻译： LC液箱结构。该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

63. 发明授权

US07129561B2 Tri-metal and dual-metal stacked inductors 有权
标题翻译：三金属和双金属堆叠电感器
公开(公告)号：US07129561B2
公开(公告)日：2006-10-31
申请号：US10707065
申请日：2003-11-19
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Robert A. Groves , Zhong-Xiang He
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Robert A. Groves , Zhong-Xiang He
IPC分类号： H01L29/00 , H01F5/00
CPC分类号： H01L28/10 , H01L23/5227 , H01L23/5228 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A high performance inductor which has a relatively low sheet resistance that can be integrated within a semiconductor interconnect structure and can be used in RF applications, including RF CMOS and SiGe technologies, is provided. The inductor is either a dual-metal inductor including a first layer of metal which serves as an upper metal wire in the semiconductor structure and a second layer of metal located directly on top of the first layer of metal, or a tri metal inductor, which includes a third layer of metal located directly on top of the second layer of metal. No vias are located between the various metal layers of the inventive inductor.
摘要翻译：提供了具有相对低的薄层电阻的高性能电感器，其可以集成在半导体互连结构内并且可以用于RF应用中，包括RF CMOS和SiGe技术。电感器是双金属电感器，其包括在半导体结构中用作上部金属线的第一金属层和位于第一金属层的顶部的第二金属层或三金属电感器，其中，包括直接位于第二金属层顶部的第三层金属。在本发明的电感器的各种金属层之间没有通孔。

64. 发明申请

US20060163688A1 MULTIPLE LAYER STRUCTURE FOR SUBSTRATE NOISE ISOLATION 有权
标题翻译：用于基层噪声隔离的多层结构
公开(公告)号：US20060163688A1
公开(公告)日：2006-07-27
申请号：US10905934
申请日：2005-01-27
申请人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L21/76 , H01L29/00 , H01L23/58 , H01L23/552
CPC分类号： H01L21/76264 , H01L23/552 , H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and the buried insulative layer combine to form a high impedance noise isolation that surrounds the protected area on all sides except one side of the protected area to isolate noise from the protected area; forming a second trench within the substrate around the first trench; and filling the second trench with a conductive material, wherein the second trench filled with the conductive material and the heavily doped layer combine to form a low impedance ground path that surrounds the high impedance noise isolation on all sides except one side of the high impedance noise isolation to isolate noise from the protected area.
摘要翻译：一种形成半导体结构的方法，包括：提供具有掩埋绝缘层和重掺杂层的衬底; 在保护区域周围形成衬底内的第一沟槽; 用绝缘材料填充第一沟槽，其中填充有绝缘材料的第一沟槽和埋入绝缘层组合形成高阻抗噪声隔离，围绕保护区域的保护区域，除了保护区域的一侧以隔离噪声保护区; 在所述衬底内围绕所述第一沟槽形成第二沟槽; 以及用导电材料填充所述第二沟槽，其中填充有所述导电材料和所述重掺杂层的所述第二沟槽组合以形成低阻抗接地路径，所述低阻抗接地路径围绕除所述高阻抗噪声的一侧之外的所有侧面上的高阻抗噪声隔离隔离隔离来自保护区的噪音。

65. 发明授权

US06913965B2 Non-Continuous encapsulation layer for MIM capacitor 失效
标题翻译： MIM电容器的非连续封装层
公开(公告)号：US06913965B2
公开(公告)日：2005-07-05
申请号：US10709133
申请日：2004-04-15
申请人： Wagdi W. Abadeer , Eric Adler , Zhong-Xiang He , Bradley Orner , Vidhya Ramachandran , Barbara A. Waterhouse , Michael Zierak
发明人： Wagdi W. Abadeer , Eric Adler , Zhong-Xiang He , Bradley Orner , Vidhya Ramachandran , Barbara A. Waterhouse , Michael Zierak
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/57
摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.
摘要翻译：本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

66. 发明申请

US20050104188A1 OPTIMUM PADSET FOR WIRE BONDING RF TECHNOLOGIES WITH HIGH-Q INDUCTORS 有权
标题翻译：用于具有高Q电感器的线束焊接RF技术的最佳焊盘
公开(公告)号：US20050104188A1
公开(公告)日：2005-05-19
申请号：US10707064
申请日：2003-11-19
申请人： Douglas Coolbaugh , Zhong-Xiang He , Wolfgang Sauter , Barbara Waterhouse
发明人： Douglas Coolbaugh , Zhong-Xiang He , Wolfgang Sauter , Barbara Waterhouse
IPC分类号： H01L23/485 , H01L23/522 , H01L21/44 , H01L23/48 , H01L23/52
CPC分类号： H01L24/05 , H01L23/5227 , H01L24/03 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48739 , H01L2224/48747 , H01L2224/48839 , H01L2224/48844 , H01L2224/48847 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/00014 , H01L2224/48824 , H01L2924/00 , H01L2224/48744
摘要： An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.
摘要翻译： RF结构包括用于引线键合的最佳焊盘和包含相对较厚的金属电感器导线的高性能电感器，两者都位于互连结构的最终互连级别的顶部。具体地，RF结构包括具有第一厚度的金属电感器线和位于其表面上的具有第二厚度的主要面积的金属接合焊盘的电介质层，其中第一厚度大于第二厚度。在本发明的RF结构中，大部分金属焊盘被减薄以进行引线接合，同时保持结构的其它区域中的全部金属线厚度用于电感器性能要求，例如低电阻率。还提供了制造上述RF结构的方法。

67. 发明申请

US20050067701A1 METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION 有权
标题翻译：金属绝缘体 - 金属电容器和制造方法
公开(公告)号：US20050067701A1
公开(公告)日：2005-03-31
申请号：US10605444
申请日：2003-09-30
申请人： Douglas Coolbaugh , Ebenezer Eshun , Jeffrey Gambino , Zhong-Xiang He , Vidhya Ramachandran
发明人： Douglas Coolbaugh , Ebenezer Eshun , Jeffrey Gambino , Zhong-Xiang He , Vidhya Ramachandran
IPC分类号： H01L21/02 , H01L21/768 , H01L23/52 , H01L21/44
CPC分类号： H01L21/7687 , H01L23/5223 , H01L23/53238 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.
摘要翻译：一种MIM电容器的方法和结构，该结构包括：电子器件，包括：形成在半导体衬底上的层间电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的上表面与所述层间电介质层的顶面形成; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。还公开了兼容的电阻器和对准标记结构。

68. 发明授权

US08842412B2 Tapered via and MIM capacitor 有权
公开(公告)号：US08842412B2
公开(公告)日：2014-09-23
申请号：US14176460
申请日：2014-02-10
申请人： James S. Dunn , Zhong-Xiang He , Anthony K. Stamper
发明人： James S. Dunn , Zhong-Xiang He , Anthony K. Stamper
IPC分类号： H01G4/30 , H01L49/02
CPC分类号： H01L28/40 , H01G4/228 , H01G4/33
摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.

69. 发明授权

US08674423B2 Semiconductor structure having vias and high density capacitors 有权
标题翻译：具有通孔和高密度电容器的半导体结构
公开(公告)号：US08674423B2
公开(公告)日：2014-03-18
申请号：US13302168
申请日：2011-11-22
申请人： David S. Collins , Kai D. Feng , Zhong-Xiang He , Peter J. Lindgren , Robert M. Rassel
发明人： David S. Collins , Kai D. Feng , Zhong-Xiang He , Peter J. Lindgren , Robert M. Rassel
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
摘要翻译：制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。第一和第二沟槽在衬底中具有不同的深度。

70. 发明授权

US08649153B2 Tapered via and MIM capacitor 有权
标题翻译：锥形通孔和MIM电容器
公开(公告)号：US08649153B2
公开(公告)日：2014-02-11
申请号：US13096850
申请日：2011-04-28
申请人： James Stuart Dunn , Zhong-Xiang He , Anthony Kendall Stamper
发明人： James Stuart Dunn , Zhong-Xiang He , Anthony Kendall Stamper
IPC分类号： H01G4/30
CPC分类号： H01L28/40 , H01G4/228 , H01G4/33
摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.
摘要翻译：描述了一种片式电容器和互连布线，其集成了金属绝缘体金属（MIM）电容器，锥形通孔和通孔，其在集成电路中耦合到电容器的顶部和底部电极中的一个或两个。描述了有形地体现在机器可读介质中的设计结构，其包括在集成电路中定义MIM电容器，锥形通孔，通孔和布线电平的计算机可读代码。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式