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61. 发明授权

US07800405B2 Passgate structures for use in low-voltage applications 有权
标题翻译： Passgate结构用于低压应用
公开(公告)号：US07800405B2
公开(公告)日：2010-09-21
申请号：US12484665
申请日：2009-06-15
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
摘要翻译：提出了用于低压系统的增强型门控结构，其中Vt对单晶闸管通道通过的信号范围的影响减小。在一种布置中，通过应用较高的VGATE来提高通过NMOS通道传播的信号的VGATE-Vt极限; 在另一种布置中，Vt被降低。传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

62. 发明授权

US07605603B1 User-accessible freeze-logic for dynamic power reduction and associated methods 有权
标题翻译：用户可访问的冻结逻辑，用于动态功率降低和相关方法
公开(公告)号：US07605603B1
公开(公告)日：2009-10-20
申请号：US12040100
申请日：2008-02-29
申请人： Michael D. Hutton , Andy L. Lee
发明人： Michael D. Hutton , Andy L. Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , H03K19/17784
摘要： A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.
摘要翻译：可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

63. 发明授权

US07504855B1 Multiple data rate memory interface architecture 有权
标题翻译：多数据速率存储器接口架构
公开(公告)号：US07504855B1
公开(公告)日：2009-03-17
申请号：US11672438
申请日：2007-02-07
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173 , G11C7/00
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
摘要翻译：本发明提供了一种用于在可编程逻辑器件中实现高速多数据速率接口架构的DQS总线。 DQS总线在至少一个数据选通电路和多个I / O寄存器块之间具有平衡树结构。

64. 发明授权

US07432734B2 Versatile logic element and logic array block 有权
公开(公告)号：US07432734B2
公开(公告)日：2008-10-07
申请号：US11743625
申请日：2007-05-02
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

65. 发明授权

US07112992B1 Configuration shift register 有权
标题翻译：配置移位寄存器
公开(公告)号：US07112992B1
公开(公告)日：2006-09-26
申请号：US11008080
申请日：2004-12-08
申请人： Mario Guzman , Chris Lane , Andy L. Lee , Ninh Ngo
发明人： Mario Guzman , Chris Lane , Andy L. Lee , Ninh Ngo
IPC分类号： H03K19/173
CPC分类号： H03K19/17752 , H03K19/1774 , H03K19/17744 , H03K19/17756
摘要： An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.
摘要翻译：电子设备包括作为移位寄存器连接的第一多个配置元件，用于对电子设备的可编程功能的子集进行编程。可编程功能的子集可以通过将配置数据加载到第一多个配置元件中来重新编程，使得可编程功能的子集可以被重新编程，而不必重新编程电子设备的其他可编程功能。

66. 发明授权

US07010777B1 Shared lookup table enhancements for the efficient implementation of barrel shifters 失效
标题翻译：共享查找表增强了桶形移位器的有效实现
公开(公告)号：US07010777B1
公开(公告)日：2006-03-07
申请号：US10807360
申请日：2004-03-22
申请人： Michael Hutton , Andy L. Lee , Rahul Saini
发明人： Michael Hutton , Andy L. Lee , Rahul Saini
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H03K19/1736 , H03K19/17728
摘要： Additional circuitry is provided over a shared-LUT logic circuit to allow functions of different input characteristics to share a logic element which was conventionally illegal. More restrictive circuitry may be provided over a shared-LUT logic circuit to allow functions with particular input characteristics.
摘要翻译：在共享LUT逻辑电路上提供附加电路，以允许不同输入特性的功能共享通常是非法的逻辑元件。可以在共享LUT逻辑电路上提供更多限制性电路以允许具有特定输入特性的功能。

67. 发明授权

US07000161B1 Reconfigurable programmable logic system with configuration recovery mode 失效
公开(公告)号：US07000161B1
公开(公告)日：2006-02-14
申请号：US10270800
申请日：2002-10-11
申请人： Tim Allen , Michael Fairman , Mario Guzman , Bryan Hoyer , Chris Lane , Kerry Veenstra , Keith Duwel , Andy L. Lee
发明人： Tim Allen , Michael Fairman , Mario Guzman , Bryan Hoyer , Chris Lane , Kerry Veenstra , Keith Duwel , Andy L. Lee
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

68. 发明授权

US06970014B1 Routing architecture for a programmable logic device 失效
标题翻译：可编程逻辑器件的路由架构
公开(公告)号：US06970014B1
公开(公告)日：2005-11-29
申请号：US10623709
申请日：2003-07-21
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Brian D. Johnson , Richard Cliff , Srinivas T. Reddy , Christopher F. Lane , Cameron R. McClintock , Vaughn Betz , Chris Wysocki , Alexander R. Marquardt
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Brian D. Johnson , Richard Cliff , Srinivas T. Reddy , Christopher F. Lane , Cameron R. McClintock , Vaughn Betz , Chris Wysocki , Alexander R. Marquardt
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides.
摘要翻译：本发明的实施例涉及在可编程逻辑器件（“PLD”）内互连诸如逻辑阵列块（“LAB”）的功能块的3边路由架构。在三面路由架构中，功能块第一侧的输入和输出连接到第一通道，功能块第二侧上的输入和输出连接到第二通道，其中第二侧与第一通道相反侧。功能块第三侧的输入和输出连接到第三个通道。与功能块的第四侧相关联的与第三侧相反的第四侧的第四通道仅耦合到第一通道和第二通道。在一种配置中，第一侧，第二侧和第三侧中的每一个上的输入和输出具有相等数量的输入和输出。在该配置中，第一通道，第二通道和第三通道中的每一个具有相同的宽度。在另一种构造中，第一侧，第二侧或第三侧中的一个上的引脚数目与另一侧上的引脚数不同。

69. 发明授权

US06798242B2 Programmable logic device with hierarchical interconnection resources 失效
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06798242B2
公开(公告)日：2004-09-28
申请号：US10426991
申请日：2003-04-29
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。本地导体与每个区域相关联，主要用于使信号进入该区域。在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

70. 发明授权

US06577160B2 Programmable logic device with hierarchical interconnection resources 有权
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06577160B2
公开(公告)日：2003-06-10
申请号：US10170026
申请日：2002-06-10
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联。本地导体与每个区域相关联。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

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