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61. 发明授权

US07696573B2 Multiple crystallographic orientation semiconductor structures 失效
标题翻译：多晶体取向半导体结构
公开(公告)号：US07696573B2
公开(公告)日：2010-04-13
申请号：US11931209
申请日：2007-10-31
申请人： Shreesh Narasimha , Paul David Agnello , Xiaomeng Chen , Judson R. Holt , Mukesh Vijay Khare , Byeong Y. Kim , Devandra K. Sadana
发明人： Shreesh Narasimha , Paul David Agnello , Xiaomeng Chen , Judson R. Holt , Mukesh Vijay Khare , Byeong Y. Kim , Devandra K. Sadana
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/00
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/1207
摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.
摘要翻译：半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

62. 发明授权

US07687804B2 Method for fabricating a semiconductor structures and structures thereof 失效
标题翻译：半导体结构的制造方法及其结构
公开(公告)号：US07687804B2
公开(公告)日：2010-03-30
申请号：US11970592
申请日：2008-01-08
申请人： Thomas N. Adam , Ashima B. Chakravarti , Eric C. T. Harley , Judson R. Holt
发明人： Thomas N. Adam , Ashima B. Chakravarti , Eric C. T. Harley , Judson R. Holt
IPC分类号： H01L29/04 , H01L31/20 , H01L31/036 , H01L31/0376
CPC分类号： H01L29/66545 , H01L21/0237 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02636 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76224 , H01L29/165 , H01L29/41783 , H01L29/66553
摘要： Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.
摘要翻译：制造具有设置在半导体结构的基板的表面上的非外延薄膜的半导体结构的方法; 并且公开了由其形成的半导体结构。该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。表面可以是非结晶介电材料或结晶材料。非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。

63. 发明授权

US07682915B2 Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance 有权
标题翻译：具有非常低温选择性外延的预外延一次性间隔物集成方案，以提高器件性能
公开(公告)号：US07682915B2
公开(公告)日：2010-03-23
申请号：US12100644
申请日：2008-04-10
申请人： Huajie Chen , Judson R. Holt , Kern Rim , Dominic J. Schepis
发明人： Huajie Chen , Judson R. Holt , Kern Rim , Dominic J. Schepis
IPC分类号： H01L21/336
CPC分类号： H01L21/823864 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.
摘要翻译：本发明的实施例提供了一种用于具有非常低的温度选择性外延的预外延一次性间隔物集成方案的方法等，以增强器件性能。更具体地，一种方法是通过在衬底上形成第一栅极和第二栅极开始的。接下来，在第一和第二栅极上形成氧化物层; 并且在氧化物层上形成氮化物层。接近第一栅极的氮化物层的部分，靠近第一栅极的氧化物层的部分以及靠近第一栅极的衬底的部分被去除，以便形成靠近第一栅极的源极和漏极。接下来，该方法去除氮化物层的剩余部分，包括暴露氧化物层的剩余部分。去除氮化物层的剩余部分仅暴露氧化物层和源极和漏极凹槽的剩余部分。

64. 发明授权

US07674720B2 Stacking fault reduction in epitaxially grown silicon 失效
标题翻译：堆积外延生长硅中的断层减少
公开(公告)号：US07674720B2
公开(公告)日：2010-03-09
申请号：US12131214
申请日：2008-06-02
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.
摘要翻译：公开了用于提供用于混合表面取向结构的堆叠故障减少的外延生长的硅的方法。在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫并且在开口中外延生长硅。由于底切产生的负斜率，硅片堆积层错误大大减少。

65. 发明申请

US20090181508A1 Method and Structure For NFET With Embedded Silicon Carbon 审中-公开
标题翻译：具有嵌入式硅碳的NFET的方法和结构
公开(公告)号：US20090181508A1
公开(公告)日：2009-07-16
申请号：US12014934
申请日：2008-01-16
申请人： Judson R. Holt , Yaocheng Liu , Kern Rim
发明人： Judson R. Holt , Yaocheng Liu , Kern Rim
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/324 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method forms a gate stack over a channel region of a substrate and then forms disposable spacers on sides of the gate stack. Trenches are then recessed in regions of the substrate not protected by the gate stack and the disposable spacers. Carbon-doped Silicon lattice structures are then formed in the trenches. During the forming of the Carbon-doped Silicon lattice structures Carbon atoms can be positioned in any substitutional sites within the lattice structures. The Carbon-doped Silicon lattice structures are then amorphized by implantation of an amorphizing species. An annealing process then recrystallizes the amorphized regions by solid-phase epitaxy regrowth to form the source and drain regions. During the annealing, a majority of Carbon atoms are substitutionally incorporated into a Silicon lattice of the source and drain regions to provide tensile stress to the channel region.
摘要翻译：一种方法在衬底的通道区域上形成栅极堆叠，然后在栅极叠层的侧面上形成一次性间隔物。沟槽然后凹陷在不被栅极堆叠和一次性间隔件保护的衬底的区域中。然后在沟槽中形成碳掺杂的硅晶格结构。在形成碳掺杂硅晶格结构期间，碳原子可以位于晶格结构内的任何取代位置。然后通过植入非晶化物质将碳掺杂的硅晶格结构非晶化。退火工艺然后通过固相外延再生长再结晶非晶化区域以形成源区和漏区。在退火期间，大多数碳原子被替代地并入到源极和漏极区域的硅晶格中，以向沟道区域提供拉伸应力。

66. 发明授权

US07528050B2 High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods 失效
标题翻译：具有应力诱导材料的SOI衬底上的高性能场效应晶体管作为掩埋绝缘体和方法
公开(公告)号：US07528050B2
公开(公告)日：2009-05-05
申请号：US12115106
申请日：2008-05-05
申请人： Judson R. Holt , Qiqing C. Ouyang
发明人： Judson R. Holt , Qiqing C. Ouyang
IPC分类号： H01L21/46
CPC分类号： H01L29/78 , H01L21/76254 , H01L27/1203 , H01L27/1207 , H01L29/7846
摘要： The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.
摘要翻译：本发明提供了一种半导体结构，其包括绝缘体（SOI）上的高性能场效应晶体管（FET），其绝缘体是预选几何形状的应力诱导材料。这种结构可以实现单轴应力的性能提高，并且通道中的应力不依赖于局部触点的布局设计。广义而言，本发明涉及一种包括上半导体层和底半导体层的半导体结构，其中所述上半导体层通过具有预选的应力诱导绝缘体在至少一个区域中与所述底部半导体层分离几何形状，所述应力诱导绝缘子在上半导体层上施加应变。

67. 发明授权

US07485524B2 MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same 失效
标题翻译：包括具有倾斜的上表面的源/漏区的MOSFET及其制造方法
公开(公告)号：US07485524B2
公开(公告)日：2009-02-03
申请号：US11425542
申请日：2006-06-21
申请人： Zhijiong Luo , Yung F. Chong , Judson R. Holt , Zhao Lun , Huilong Zhu
发明人： Zhijiong Luo , Yung F. Chong , Judson R. Holt , Zhao Lun , Huilong Zhu
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.
摘要翻译：本发明涉及包括源极和漏极（S / D）区域的改进的金属氧化物半导体场效应晶体管（MOSFET）器件，其具有相对于衬底表面倾斜的上表面。这样的S / D区域可以包括在半导体衬底中的表面凹槽中外延生长的半导体结构。优选的表面凹部具有平行于基板表面的底表面，该底表面沿着第一组等效晶面中的一个取向，并且沿着第二不同组的等效晶面定向的一个或多个侧壁表面。 S / D区域的倾斜上表面用于改善沟道区域中的应力分布以及降低MOSFET的接触电阻。具有倾斜的上表面的这种S / D区域可以容易地通过半导体衬底的晶体蚀刻形成，随后半导体材料的外延生长。

68. 发明申请

US20080116484A1 METHOD OF ENHANCING HOLE MOBILITY 有权
标题翻译：增加孔移动性的方法
公开(公告)号：US20080116484A1
公开(公告)日：2008-05-22
申请号：US11561496
申请日：2006-11-20
申请人： Henry K. Utomo , Judson R. Holt , Haining S. Yang
发明人： Henry K. Utomo , Judson R. Holt , Haining S. Yang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/78687
摘要： A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second silicon layer comprise the same crystalline orientation. The device further includes a graded germanium layer on the first silicon layer, wherein the graded germanium layer contacts a spacer and the first silicon layer and does not contact the oxide layer. A lower portion of the graded germanium layer comprises a higher concentration of germanium than an upper portion of the graded germanium layer, wherein a top surface of the graded germanium layer lacks germanium.
摘要翻译：提供一种半导体器件，其包括位于氧化物层之上的第一硅层和第二硅层上的氧化物层，其中氧化物层位于第一硅层和第二硅层之间。第一硅层和第二硅层包含相同的晶体取向。所述器件还包括在所述第一硅层上的分级锗层，其中所述分级锗层接触间隔物和所述第一硅层并且不接触所述氧化物层。分级锗层的下部包含比分级锗层的上部更高浓度的锗，其中分级锗层的顶表面缺少锗。

69. 发明申请

US20080006854A1 MOSFETS COMPRISING SOURCE/DRAIN REGIONS WITH SLANTED UPPER SURFACES, AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：包含上述上表面的源/漏区域的MOSFETs及其制造方法
公开(公告)号：US20080006854A1
公开(公告)日：2008-01-10
申请号：US11425542
申请日：2006-06-21
申请人： Zhijiong Luo , Yung F. Chong , Judson R. Holt , Zhao Lun , Huilong Zhu
发明人： Zhijiong Luo , Yung F. Chong , Judson R. Holt , Zhao Lun , Huilong Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7848 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.
摘要翻译：本发明涉及包括源极和漏极（S / D）区域的改进的金属氧化物半导体场效应晶体管（MOSFET）器件，其具有相对于衬底表面倾斜的上表面。这样的S / D区域可以包括在半导体衬底中的表面凹槽中外延生长的半导体结构。优选的表面凹部具有平行于基板表面的底表面，该底表面沿着第一组等效晶面中的一个取向，并且沿着第二不同组的等效晶面定向的一个或多个侧壁表面。 S / D区域的倾斜上表面用于改善沟道区域中的应力分布以及降低MOSFET的接触电阻。具有倾斜的上表面的这种S / D区域可以容易地通过半导体衬底的晶体蚀刻形成，随后半导体材料的外延生长。

70. 发明申请

US20070275510A1 METAL OXIDE FIELD EFFECT TRANSISTOR WITH A SHARP HALO AND A METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有夏普HALO的金属氧化物场效应晶体管和形成晶体管的方法
公开(公告)号：US20070275510A1
公开(公告)日：2007-11-29
申请号：US11420318
申请日：2006-05-25
申请人： Huajie Chen , Judson R. Holt , Rangarajan Jagannathan , Wesley C. Natzle , Michael R. Sievers , Richard S. Wise
发明人： Huajie Chen , Judson R. Holt , Rangarajan Jagannathan , Wesley C. Natzle , Michael R. Sievers , Richard S. Wise
IPC分类号： H01L21/8232 , H01L21/8234 , H01L21/335
CPC分类号： H01L29/66636 , H01L29/6659 , H01L29/7833
摘要： Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.
摘要翻译：公开了具有限定的限定的卤素的MOSFET的实施例，其限定的源极/漏极扩展部分以及形成MOSFET的方法。蚀刻半导体层以形成切割栅极介电层的凹部。低能量植入物形成晕轮。然后，执行COR预清洁，并且通过外延沉积填充凹部。外延可以被原位掺杂或随后植入以形成源/漏扩展。或者，蚀刻之后紧接着是COR预清洁，随后进行外延沉积以填充凹部。在外延沉积工艺期间，沉积的材料被掺杂以形成原位掺杂的光晕，然后切换掺杂剂以形成邻近光晕的原位掺杂的源极/漏极延伸。或者，在形成原位掺杂的光晕之后，进行沉积工艺而没有掺杂剂，并且使用注入来形成源极/漏极延伸部。

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