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61. 发明授权

US08703592B2 Methods of forming semiconductor devices having faceted semiconductor patterns 有权
标题翻译：形成具有刻面半导体图案的半导体器件的方法
公开(公告)号：US08703592B2
公开(公告)日：2014-04-22
申请号：US13052460
申请日：2011-03-21
申请人： Myung-Sun Kim , Dong-Suk Shin , Dong-Hyuk Kim , Yong-Joo Lee , Hoi-Sung Chung
发明人： Myung-Sun Kim , Dong-Suk Shin , Dong-Hyuk Kim , Yong-Joo Lee , Hoi-Sung Chung
IPC分类号： H01L21/425
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： Provided are methods of forming semiconductor devices. A method may include preparing a semiconductor substrate including a first region and a second region adjacent the first region. The method may also include forming sacrificial pattern covering the second region and exposing the first region. The method may further include forming a capping layer including a faceted sidewall on the first region using selective epitaxial growth (SEG). The faceted sidewall may be separate from the sacrificial pattern. The sacrificial pattern may be removed. Impurity ions may be implanted into the semiconductor substrate.
摘要翻译：提供了形成半导体器件的方法。一种方法可以包括制备包括第一区域和邻近第一区域的第二区域的半导体衬底。该方法还可以包括形成覆盖第二区域并暴露第一区域的牺牲图案。该方法还可以包括使用选择性外延生长（SEG）在第一区域上形成包括有侧壁的覆盖层。小面侧壁可以与牺牲图案分离。可以去除牺牲图案。杂质离子可以注入到半导体衬底中。

62. 发明授权

US08648424B2 Semiconductor device including transistors having embedded source/drain regions each including upper and lower main layers comprising germanium 有权
标题翻译：半导体器件包括具有嵌入的源/漏区的晶体管，每个晶体管包括包含锗的上和下主层
公开(公告)号：US08648424B2
公开(公告)日：2014-02-11
申请号：US13600375
申请日：2012-08-31
申请人： Hoi-Sung Chung , Dong-Hyuk Kim , Myung-Sun Kim , Dong-Suk Shin
发明人： Hoi-Sung Chung , Dong-Hyuk Kim , Myung-Sun Kim , Dong-Suk Shin
IPC分类号： H01L21/70
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a substrate having a channel region, a gate insulation layer on the channel region, a gate electrode on the gate insulation layer, and source and drain regions in recesses in the substrate on both sides of the channel region, respectively. The source and drain regions include a lower main layer whose bottom surface is located at level above the bottom of a recess and lower than that of the bottom surface of the gate insulation layer, and a top surface no higher than the level of the bottom surface of the gate insulation layer, and an upper main layer contacting the lower main layer and whose top surface extends to a level higher than that of the bottom surface of the gate insulation layer, and in which the lower layer has a Ge content higher than that of the upper layer.
摘要翻译：半导体器件包括具有沟道区的衬底，沟道区上的栅极绝缘层，栅极绝缘层上的栅电极，以及沟道区两侧的衬底中的凹槽中的源极和漏极区。源极和漏极区域包括下表面位于凹槽底部的平面以上并且低于栅极绝缘层的底表面的下主层，以及不高于底表面的高度的顶表面的栅极绝缘层的上部主层和与下部主层接触的上部主层，其上表面延伸到比栅极绝缘层的底面高的水平，并且其中下层的Ge含量高于栅极绝缘层的底面。的上层。

63. 发明授权

US08502286B2 Etch stop layers and methods of forming the same 有权
标题翻译：蚀刻停止层及其形成方法
公开(公告)号：US08502286B2
公开(公告)日：2013-08-06
申请号：US12841245
申请日：2010-07-22
申请人： Ha-Jin Lim , Dong-Suk Shin , Pan-Kwi Park
发明人： Ha-Jin Lim , Dong-Suk Shin , Pan-Kwi Park
IPC分类号： H01L29/76
CPC分类号： H01L29/76 , H01L21/823807 , H01L27/092 , H01L29/7843
摘要： A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.
摘要翻译：半导体器件包括MOSFET和设置在MOSFET上的多个应力层，其中应力层包括设置在MOSFET上的第一应力层和设置在第一应力层上的第二应力层，第一应力层具有第一应力层应力和第二应力层具有第二应力，并且第一应力不同于第二应力。

64. 发明申请

US20120164807A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120164807A1
公开(公告)日：2012-06-28
申请号：US13408311
申请日：2012-02-29
申请人： Min-Chul SUN , Dong-Suk Shin , Jung-Deog Lee
发明人： Min-Chul SUN , Dong-Suk Shin , Jung-Deog Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/088 , H01L21/76897 , H01L29/665 , H01L29/6656
摘要： A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region.
摘要翻译：一种半导体器件及其制造方法，半导体器件包括半导体衬底，半导体衬底上的栅极绝缘层，具有侧壁的栅电极，栅极绝缘层，栅电极的侧壁上的第一间隔物，源极/漏极区域，与侧壁对准，栅极上的硅化物层，源极/漏极区域上的硅化物层，以及覆盖第一间隔物和硅化物层的表面的端部的第二间隔物，源极漏极区域。

65. 发明授权

US08207772B2 Duty detection circuit and duty cycle correction circuit including the same 失效
标题翻译：占空比检测电路和占空比校正电路包括相同
公开(公告)号：US08207772B2
公开(公告)日：2012-06-26
申请号：US12832092
申请日：2010-07-08
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H03K3/017
CPC分类号： G11C7/22 , G11C7/222 , H03K5/1565 , H03K9/08
摘要： A duty cycle correction circuit includes a duty adjustment circuit configured to generate an output clock by adjusting a duty cycle of an input clock in response to a duty adjustment code, a duty detection circuit configured to measure a difference between a width of a high pulse and a width of a low pulse of the output clock at each update period, and generate a duty detection code corresponding to the measured value, an accumulation circuit configured to generate the duty adjustment code by accumulating a value of the duty detection code outputted at each update period, and a toggling number adjustment circuit configured to adjust a toggling number of the output clock, which adjustment determines the update period, according to a frequency of the output clock.
摘要翻译：占空比校正电路包括占空比调整电路，其被配置为通过响应于占空比调整代码调整输入时钟的占空比来产生输出时钟;占空比检测电路，被配置为测量高脉冲宽度与在每个更新周期的输出时钟的低脉冲的宽度，并且生成与测量值相对应的占空比检测码;累加电路，被配置为通过累加在每次更新时输出的占空比检测码的值来生成占空比调整码周期，以及切换数量调整电路，被配置为根据输出时钟的频率来调整输出时钟的切换次数，该调整确定更新周期。

66. 发明授权

US07868673B2 Power-down mode control apparatus and DLL circuit having the same 有权
标题翻译：掉电模式控制装置和DLL电路具有相同的功能
公开(公告)号：US07868673B2
公开(公告)日：2011-01-11
申请号：US12698606
申请日：2010-02-02
申请人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
发明人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

67. 发明申请

US20100081246A1 Method of manufacturing a semiconductor 审中-公开
标题翻译：制造半导体的方法
公开(公告)号：US20100081246A1
公开(公告)日：2010-04-01
申请号：US12585862
申请日：2009-09-28
申请人： Dong-Suk Shin , Joo-Won Lee
发明人： Dong-Suk Shin , Joo-Won Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/265 , H01L21/823864 , H01L29/66507 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device and a method of manufacturing a semiconductor device, the method including forming a gate insulation layer and a gate electrode on a substrate, forming a silicon nitride layer on the gate electrode and the gate insulation layer, partially implanting ions into the silicon nitride layer to convert an upper portion of the silicon nitride layer into a treated silicon layer including the ions, etching the treated silicon layer to form a spacer on a sidewall of the gate electrode, and forming an impurity region in the substrate adjacent to the gate electrode.
摘要翻译：一种半导体器件和半导体器件的制造方法，该方法包括在衬底上形成栅绝缘层和栅电极，在栅电极和栅极绝缘层上形成氮化硅层，将离子部分地注入到氮化硅层，将氮化硅层的上部转换为包含离子的经处理的硅层，蚀刻经处理的硅层，以在栅电极的侧壁上形成间隔物，以及在与栅电极相邻的衬底中形成杂质区。

68. 发明授权

US07683684B2 Power-down mode control apparatus and DLL circuit having the same 有权
标题翻译：掉电模式控制装置和DLL电路具有相同的功能
公开(公告)号：US07683684B2
公开(公告)日：2010-03-23
申请号：US12175212
申请日：2008-07-17
申请人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
发明人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

69. 发明授权

US07582535B2 Method of forming MOS transistor having fully silicided metal gate electrode 有权
标题翻译：形成具有完全硅化金属栅电极的MOS晶体管的方法
公开(公告)号：US07582535B2
公开(公告)日：2009-09-01
申请号：US11158978
申请日：2005-06-22
申请人： Seung-Hwan Lee , Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee
发明人： Seung-Hwan Lee , Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions. Respective desired thicknesses of the gate-reduced pattern and the elevated source and drain regions may be obtained using an etch selectivity between the poly-crystalline semiconductor layer and the single-crystalline semiconductor layer. A silicidation process is applied to the semiconductor substrate where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.
摘要翻译：提供制造具有完全硅化金属栅电极的MOS晶体管的方法。该方法包括在半导体衬底的预定区域中形成隔离层以限定有源区。形成了跨越有源区域的绝缘栅极图案。在栅极图案的侧壁上形成间隔物。施加选择性外延生长工艺以在栅极图案上形成半导体层，并且在栅极图案的两侧形成半导体层。在这种情况下，在栅极图案上形成多晶半导体层，同时在栅极图案的两侧的有源区同时形成单晶半导体层。选择性地蚀刻半导体层以形成栅极减小图案和升高的源极和漏极区域。可以使用多晶半导体层和单晶半导体层之间的蚀刻选择性来获得栅极减小图案和升高的源极和漏极区域的各种期望厚度。将硅化处理应用于形成栅极减少图案的半导体衬底，以同时形成完全硅化的金属栅电极和升高的源极和漏极硅化物层。

70. 发明申请

US20090032881A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME IN WHICH A MOBILITY CHANGE OF THE MAJOR CARRIER IS INDUCED THROUGH STRESS APPLIED TO THE CHANNEL 审中-公开
标题翻译：半导体器件及其制造方法，通过应用于通道的应力引起主要载波的移动性变化
公开(公告)号：US20090032881A1
公开(公告)日：2009-02-05
申请号：US12165999
申请日：2008-07-01
申请人： Joo-Won Lee , Dong-Suk Shin , Tae-Gyun Kim
发明人： Joo-Won Lee , Dong-Suk Shin , Tae-Gyun Kim
IPC分类号： H01L27/118 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/6653 , H01L29/7833 , H01L29/7843 , H01L29/7847
摘要： A semiconductor device includes a semiconductor substrate, a gate structure formed on the semiconductor substrate, wherein the gate structure includes a gate electrode formed on the semiconductor substrate and spacers formed on sidewalls of the gate electrode, source/drain regions formed in the semiconductor substrate on both sides of the gate structure, and an etch stop layer, which is formed on the gate structure, and includes a first region formed on the spacers and a second region formed on the gate electrode, wherein the thickness of the first region is about 85% that of the thickness of the second region or less.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的栅极结构，其中栅极结构包括形成在半导体衬底上的栅电极和形成在栅电极的侧壁上的间隔物，形成在半导体衬底中的源/漏区栅极结构的两侧以及蚀刻停止层，其形成在栅极结构上，并且包括形成在间隔物上的第一区域和形成在栅电极上的第二区域，其中第一区域的厚度为约85 第二区域的厚度以下的％以下。

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