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61. 发明申请

US20100015790A1 TiC AS A THERMALLY STABLE p-METAL CARBIDE ON HIGH k SiO2 GATE STACKS 有权
标题翻译： TiC作为高k SiO 2栅极堆叠上的耐热稳定的p金属碳化物
公开(公告)号：US20100015790A1
公开(公告)日：2010-01-21
申请号：US12541575
申请日：2009-08-14
申请人： Alessandro C. Callegari , Michael A. Gribelyuk , Dianne L. Lacey , Fenton R. McFeely , Katherine L. Saenger , Sufi Zafar
发明人： Alessandro C. Callegari , Michael A. Gribelyuk , Dianne L. Lacey , Fenton R. McFeely , Katherine L. Saenger , Sufi Zafar
IPC分类号： H01L21/28 , C23C14/34
CPC分类号： H01L29/4966 , C23C14/0036 , C23C14/0635 , H01L21/28088 , H01L29/513 , H01L29/517 , H01L29/665
摘要： A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device.
摘要翻译：提供了包含TiC的复合金属，其是在包括高k电介质和界面层的栅极堆叠上具有约4.75至约5.3，优选约5e的功函数的功函数的热电稳定的p型金属，以及制造TiC复合金属的方法。此外，本发明的TiC金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许在p金属氧化物半导体（pMOS）器件中非常有侵蚀性的等效氧化物厚度（EOT）和反型层厚度缩小至低于Å 。

62. 发明申请

US20080303068A1 FIELD EFFECT TRANSISTOR USING CARBON BASED STRESS LINER 有权
标题翻译：使用碳基应力衬里的场效应晶体管
公开(公告)号：US20080303068A1
公开(公告)日：2008-12-11
申请号：US11760030
申请日：2007-06-08
申请人： Alfred Grill , Son Nguyen , Katherine L. Saenger
发明人： Alfred Grill , Son Nguyen , Katherine L. Saenger
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823807 , H01L27/092 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A stress liner for use within a semiconductor structure that includes a field effect device has a dielectric constant less than about 7 and a compressive stress greater than about 5 GPa. The stress liner may be formed of a carbon based material, preferably a tetrahedral amorphous carbon (ta-C) material including at least about 60 atomic percent carbon and no greater than C about 40 atomic percent hydrogen. The carbon based material may be either a dielectric material, or given appropriate additional dielectric isolation structures, a semiconductor material. In particular, a ta-C stress liner may be formed using a filtered cathodic vacuum arc (FCVA) physical vapor deposition (PVD) method.
摘要翻译：在包括场效应器件的半导体结构内使用的应力衬垫具有小于约7的介电常数和大于约5GPa的压缩应力。应力衬垫可以由碳基材料形成，优选地包括至少约60原子％的碳和不大于约40原子％的氢的四面体无定形碳（ta-C）材料。碳基材料可以是介电材料，也可以是适当的另外的绝缘隔离结构，半导体材料。特别地，可以使用过滤的阴极真空电弧（FCVA）物理气相沉积（PVD）方法形成ta-C应力衬垫。

63. 发明授权

US07449767B2 Mixed orientation and mixed material semiconductor-on-insulator wafer 有权
标题翻译：混合取向和混合材料绝缘体上半导体晶片
公开(公告)号：US07449767B2
公开(公告)日：2008-11-11
申请号：US11522905
申请日：2006-09-19
申请人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
发明人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
IPC分类号： H01L29/04
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
摘要翻译：本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。还公开了用于制造本发明的不同实施例的方法和过程。

64. 发明申请

US20080258220A1 ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS 有权
标题翻译：用于改进现场效应晶体管的原位或原位热处理组合的离子植入
公开(公告)号：US20080258220A1
公开(公告)日：2008-10-23
申请号：US12128040
申请日：2008-05-28
申请人： Stephen W. Bedell , Joel P. De Souza , Zhibin Ren , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi
发明人： Stephen W. Bedell , Joel P. De Souza , Zhibin Ren , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi
IPC分类号： H01L27/12 , H01L21/8234
CPC分类号： H01L29/66628 , H01L21/26513 , H01L21/324 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78684 , Y10S438/909 , Y10S438/943
摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.
摘要翻译：本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源极/漏极（S / D）区域的潜在问题）的方法，以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

65. 发明申请

US20080171426A1 UNIAXIAL STRAIN RELAXATION OF BIAXIAL-STRAINED THIN FILMS USING ION IMPLANTATION 失效
标题翻译：使用离子植入的双应变薄膜的单轴应变松弛
公开(公告)号：US20080171426A1
公开(公告)日：2008-07-17
申请号：US11622524
申请日：2007-01-12
申请人： Zhibin Ren , Katherine L. Saenger , Haizhou Yin
发明人： Zhibin Ren , Katherine L. Saenger , Haizhou Yin
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/823807 , H01L29/78 , H01L29/7848 , Y10S438/938
摘要： A method for achieving uniaxial strain on originally biaxial-strained thin films after uniaxial strain relaxation induced by ion implantation is provided. The biaxial-strained thin film receives ion implantation after being covered by a patterned implant block structure. The strain in the uncovered region is relaxed by ion implantation, which induces the lateral strain relaxation in the covered region. When the implant block structure is narrow (dimension is comparable to the film thickness), the original biaxial strain will relax uniaxially in the lateral direction.
摘要翻译：提供了一种通过离子注入诱发的单轴应变松弛之后在原始双轴应变薄膜上实现单轴应变的方法。双轴应变薄膜在被图案化的植入物块结构覆盖之后接收离子注入。未覆盖区域的应变通过离子注入而松弛，这引起覆盖区域的横向应变弛豫。当植入物块结构窄（尺寸与膜厚度相当）时，原始双轴应变将在横向方向上单轴弛豫。

66. 发明授权

US06187679B1 Low temperature formation of low resistivity titanium silicide 失效
标题翻译：低电阻率硅化钛的低温形成
公开(公告)号：US06187679B1
公开(公告)日：2001-02-13
申请号：US08807739
申请日：1997-02-26
申请人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
发明人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
IPC分类号： H01L2144
CPC分类号： C30B1/02 , C30B29/10 , H01L21/28518 , H01L29/665
摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600-700° C.
摘要翻译：低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600-700℃之间

67. 发明授权

US5828131A Low temperature formation of low resistivity titanium silicide 失效
标题翻译：低电阻率硅化钛的低温形成
公开(公告)号：US5828131A
公开(公告)日：1998-10-27
申请号：US586046
申请日：1996-01-16
申请人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
发明人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
IPC分类号： C23C20/02 , C30B1/02 , H01L21/28 , H01L21/285 , H01L21/336 , H01L29/45
CPC分类号： C30B1/02 , C30B29/10 , H01L21/28518 , H01L29/665
摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900.degree. C., and more preferably between about 600.degree.-700.degree. C.
摘要翻译：低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600℃至700℃之间。

68. 发明授权

US5585998A Isolated sidewall capacitor with dual dielectric 失效
标题翻译：隔离侧壁电容器，双电介质
公开(公告)号：US5585998A
公开(公告)日：1996-12-17
申请号：US577166
申请日：1995-12-22
申请人： David E. Kotecki , William H. Ma , Katherine L. Saenger
发明人： David E. Kotecki , William H. Ma , Katherine L. Saenger
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/115 , H01G4/06 , H01G4/008 , H01G7/00
CPC分类号： H01L27/11502 , H01L27/10852 , H01L28/55 , Y10T29/435
摘要： An isolated sidewall capacitor with dual dielectric, which includes two capacitors. The first capacitor includes a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening. The second capacitor includes the second conductor, a first non-conductor disposed over the top portion of the second conductor, a third conductor disposed over the first non-conductor, and the third conductor electrically connected to the first conductor. A second non-conductor isolates the first conductor from the second conductor.
摘要翻译：具有双电介质的隔离侧壁电容器，其包括两个电容器。所述第一电容器包括位于衬底顶部的第一导体，位于所述第一导体顶部并基本上与所述第一导体对准的第一非导体，所述第一导体和第一非导体具有形成在其中的第一开口，非导电侧壁在第一开口中形成的间隔件，其中形成有第二开口的非导电侧壁隔离件和形成在第二开口中的第二导体。第二电容器包括第二导体，设置在第二导体的顶部上的第一非导体，设置在第一非导体上的第三导体，以及电连接到第一导体的第三导体。第二非导体将第一导体与第二导体隔离。

69. 发明授权

US08298923B2 Germanium-containing release layer for transfer of a silicon layer to a substrate 有权
标题翻译：含锗释放层，用于将硅层转移到基底
公开(公告)号：US08298923B2
公开(公告)日：2012-10-30
申请号：US12912940
申请日：2010-10-27
申请人： Stephen W. Bedell , Keith E. Fogel , Daniel A. Inns , Jeehwan Kim , Devendra K. Sadana , Katherine L. Saenger
发明人： Stephen W. Bedell , Keith E. Fogel , Daniel A. Inns , Jeehwan Kim , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/20
CPC分类号： H01L21/0262 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02664 , H01L21/76254
摘要： A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.
摘要翻译：含锗层沉积在单一晶体体硅衬底上，包括足以以原子浓度掺入1％-50％的氧的氧分压水平。含锗层的厚度优选被限制以保持与底层硅衬底的一定程度的外延对准。任选地，可以在含锗层上生长或替代含锗层。随后将至少部分结晶的硅层沉积在含锗层上。手柄基板结合到至少部分结晶的硅层。本体硅衬底，含锗层，至少部分结晶的硅层和处理衬底的组件在含锗层内被切割以提供复合衬底，该复合衬底包括处理衬底和至少部分结晶的硅层。去除复合衬底上任何剩余的含锗层。

70. 发明申请

US20120104390A1 Germanium-Containing Release Layer For Transfer of a Silicon Layer to a Substrate 有权
标题翻译：含锗的释放层用于将硅层转移到基板
公开(公告)号：US20120104390A1
公开(公告)日：2012-05-03
申请号：US12912940
申请日：2010-10-27
申请人： Stephen W. Bedell , Keith E. Fogel , Daniel A. Inns , Jeehwan Kim , Devendra K. Sadana , Katherine L. Saenger
发明人： Stephen W. Bedell , Keith E. Fogel , Daniel A. Inns , Jeehwan Kim , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L29/04 , H01L21/20
CPC分类号： H01L21/0262 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02664 , H01L21/76254
摘要： A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.
摘要翻译：含锗层沉积在单一晶体体硅衬底上，包括足以以原子浓度掺入1％-50％的氧的氧分压水平。含锗层的厚度优选被限制以保持与底层硅衬底的一定程度的外延对准。任选地，可以在含锗层上生长或替代含锗层。随后将至少部分结晶的硅层沉积在含锗层上。手柄基板结合到至少部分结晶的硅层。本体硅衬底，含锗层，至少部分结晶的硅层和处理衬底的组件在含锗层内被切割以提供复合衬底，该复合衬底包括处理衬底和至少部分结晶的硅层。去除复合衬底上任何剩余的含锗层。

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