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1. 发明申请

US20080258220A1 ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS 有权
标题翻译：用于改进现场效应晶体管的原位或原位热处理组合的离子植入
公开(公告)号：US20080258220A1
公开(公告)日：2008-10-23
申请号：US12128040
申请日：2008-05-28
申请人： Stephen W. Bedell , Joel P. De Souza , Zhibin Ren , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi
发明人： Stephen W. Bedell , Joel P. De Souza , Zhibin Ren , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi
IPC分类号： H01L27/12 , H01L21/8234
CPC分类号： H01L29/66628 , H01L21/26513 , H01L21/324 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78684 , Y10S438/909 , Y10S438/943
摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.
摘要翻译：本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源极/漏极（S / D）区域的潜在问题）的方法，以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

2. 发明申请

US20090134460A1 STRAINED SEMICONDUCTOR-ON-INSULATOR (sSOI) BY A SIMOX METHOD 有权
标题翻译：应变半导体绝缘体（sSOI）通过SIMOX方法
公开(公告)号：US20090134460A1
公开(公告)日：2009-05-28
申请号：US12363239
申请日：2009-01-30
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L27/00 , H01L21/71
CPC分类号： H01L21/76243 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
摘要翻译：提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

3. 发明授权

US07485539B2 Strained semiconductor-on-insulator (sSOI) by a simox method 有权
标题翻译：应用绝缘体半导体（sSOI）通过simox方法
公开(公告)号：US07485539B2
公开(公告)日：2009-02-03
申请号：US11332564
申请日：2006-01-13
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L21/76
CPC分类号： H01L21/76243 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
摘要翻译：提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

4. 发明申请

US20080277690A1 STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER 审中-公开
标题翻译：通过阳极氧化P +硅锗层的分级制备的绝缘硅绝缘体
公开(公告)号：US20080277690A1
公开(公告)日：2008-11-13
申请号：US12176624
申请日：2008-07-21
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L21/76259 , Y10S438/967
摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

5. 发明授权

US07172930B2 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer 有权
标题翻译：通过掩埋的p +硅锗层的阳极氧化应变的绝缘体上硅
公开(公告)号：US07172930B2
公开(公告)日：2007-02-06
申请号：US10883887
申请日：2004-07-02
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L21/00 , H01L21/84 , H01L21/331 , H01L21/8222 , H01L21/36
CPC分类号： H01L21/76259 , Y10S438/967
摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

6. 发明授权

US07897444B2 Strained semiconductor-on-insulator (sSOI) by a simox method 有权
标题翻译：应用绝缘体半导体（sSOI）通过simox方法
公开(公告)号：US07897444B2
公开(公告)日：2011-03-01
申请号：US12363239
申请日：2009-01-30
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L21/84
CPC分类号： H01L21/76243 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
摘要翻译：提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

7. 发明授权

US07592671B2 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer 失效
标题翻译：通过掩埋的p +硅锗层的阳极氧化应变的绝缘体上硅
公开(公告)号：US07592671B2
公开(公告)日：2009-09-22
申请号：US11620663
申请日：2007-01-06
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L29/94
CPC分类号： H01L21/76259 , Y10S438/967
摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

8. 发明授权

US07968459B2 Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors 有权
标题翻译：离子注入与原位或非原位热处理相结合，用于改进的场效应晶体管
公开(公告)号：US07968459B2
公开(公告)日：2011-06-28
申请号：US12128040
申请日：2008-05-28
申请人： Stephen W. Bedell , Joel P. DeSouza , Zhibin Ren , Alexander Reznicek , Devandra K. Sadana , Katherine L. Saenger , Ghavam Shahidi
发明人： Stephen W. Bedell , Joel P. DeSouza , Zhibin Ren , Alexander Reznicek , Devandra K. Sadana , Katherine L. Saenger , Ghavam Shahidi
IPC分类号： H01L21/44
CPC分类号： H01L29/66628 , H01L21/26513 , H01L21/324 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78684 , Y10S438/909 , Y10S438/943
摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.
摘要翻译：本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源/漏（S / D）区域的潜在问题）的方法，以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

9. 发明申请

US20120156861A1 QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE 审中-公开
标题翻译：使用水解硅表面和界面结合氧化物的溶解度的偶氮硅Si-Si波形粘结
公开(公告)号：US20120156861A1
公开(公告)日：2012-06-21
申请号：US13405760
申请日：2012-02-27
申请人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
发明人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/302
CPC分类号： H01L21/187 , H01L21/76251
摘要： Methods for removing or reducing the thickness of a material layer remaining at Si-Si interfaces after silicon wafer bonding. The methods include an anneal which is performed at a temperature sufficient to dissolve oxide, yet not melt silicon.
摘要翻译：在硅晶片接合之后去除或减少残留在Si-Si界面处的材料层的厚度的方法。所述方法包括在足以溶解氧化物但不熔融硅的温度下进行的退火。

10. 发明申请

US20090298258A1 QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE 有权
标题翻译：使用水解硅表面和界面结合氧化物的溶解度的偶氮硅Si-Si波形粘结
公开(公告)号：US20090298258A1
公开(公告)日：2009-12-03
申请号：US12538115
申请日：2009-08-08
申请人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
发明人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/30
CPC分类号： H01L21/187 , H01L21/76251
摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.
摘要翻译：本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与通过疏水性接合实现的性能相当的特性的结合Si-Si界面的方法。约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

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