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61. 发明授权

US06821888B2 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding 失效
标题翻译：使用导电聚合物铜/铜表面键合方法应用于IC芯片接合
公开(公告)号：US06821888B2
公开(公告)日：2004-11-23
申请号：US10076244
申请日：2002-02-13
申请人： Yakub Aliyu , Simon Chooi , Meisheng Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy
发明人： Yakub Aliyu , Simon Chooi , Meisheng Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy
IPC分类号： H01L2144
CPC分类号： H01L24/13 , H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13147 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
摘要翻译：提供了具有暴露的金属端接垫的半导体芯片，以及在其上具有对应的暴露的金属凸块的单独的基板。在暴露的金属端接垫上形成导电聚合物塞。在导电聚合物塞上形成一个符合标准的界面层。半导体芯片的导电聚合物插塞与相应的金属凸块对准。导电聚合物塞上的一致界面层与相应的金属凸块配合。一致的界面层被热分解，粘附和永久地附着导电聚合物塞与相应的金属凸块。还公开了形成和图案化羰基镍层的方法。

62. 发明授权

US06740580B1 Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier 失效
标题翻译：通过向铜扩散阻挡层添加铝层来形成铜互连的方法
公开(公告)号：US06740580B1
公开(公告)日：2004-05-25
申请号：US09389633
申请日：1999-09-03
申请人： Subhash Gupta , Chyi S. Chern , Mei Sheng Zhou
发明人： Subhash Gupta , Chyi S. Chern , Mei Sheng Zhou
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is deposited overlying the substrate layer. The dielectric layer patterned to form interconnect trenches. An optional titanium adhesion layer may be deposited. An aluminum barrier layer is deposited overlying the interior surfaces of the trenches. A second barrier layer, comprising for instance titanium and titanium nitride, is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, the second barrier layer, and the aluminum barrier layer are polished down to the top surface of the dielectric layer to define the copper interconnects, and complete the fabrication of the integrated circuit device.
摘要翻译：描述形成铜互连的方法。该方法可以用于形成单镶嵌或双镶嵌互连。向常规阻挡层添加铝阻挡层产生对铜扩散的优异屏障。提供基底层。沉积在基底层上的电介质层。图案化的电介质层形成互连沟槽。可以沉积可选的钛粘合层。覆盖在沟槽的内表面上的铝阻挡层被沉积。包含例如钛和氮化钛的第二阻挡层沉积在铝阻挡层上。沉积铜层，覆盖第二阻挡层并填充互连沟槽。铜层，第二阻挡层和铝阻挡层被抛光到介电层的顶表面以限定铜互连，并且完成集成电路器件的制造。

63. 发明授权

US06656643B2 Method of extreme ultraviolet mask engineering 有权
公开(公告)号：US06656643B2
公开(公告)日：2003-12-02
申请号：US09785116
申请日：2001-02-20
申请人： Subhash Gupta , Mei Sheng Zhou
发明人： Subhash Gupta , Mei Sheng Zhou
IPC分类号： G03F900
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/54
摘要： An EUV photolithographic mask device and a method of fabricating the same. The EUV photolithographic mask comprises a multi-layer over an EUV masking substrate and a patterned light absorbing layer formed on the multi-layer. The method comprises the steps of forming a multi-layer on an EUV mask substrate, forming a light absorbing layer on the multi-layer, and etching an opening through the light absorbing layer to the multi-layer. The light absorbing layer includes a metal selected from the group comprising nickel, chromium, cobalt, and alloys thereof, and is preferably nickel.

64. 发明授权

US06540841B1 Method and apparatus for removing contaminants from the perimeter of a semiconductor substrate 失效
标题翻译：从半导体衬底的周边去除污染物的方法和装置
公开(公告)号：US06540841B1
公开(公告)日：2003-04-01
申请号：US09607284
申请日：2000-06-30
申请人： Sudipto Ranendra Roy , Subhash Gupta , Simon Chooi , Xu Yi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Paul Kwok Keung Ho
发明人： Sudipto Ranendra Roy , Subhash Gupta , Simon Chooi , Xu Yi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Paul Kwok Keung Ho
IPC分类号： B08B700
CPC分类号： B08B1/04 , B08B3/04
摘要： A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface. After contaminants have been removed in this manner from the surface, the surface can be further cleaned by applying DI water.
摘要翻译：提供了可用于清洁半导体衬底的外边缘的新方法和装置。在本发明的第一实施例中，刷子安装在基板周围的基板的表面上，化学品通过其上安装有清洁刷的中空芯被供给到待清洁的表面。待清洁的表面以相对高的速度旋转，从而使沉积在该表面（由刷子）上的化学物质残留在表面的边缘。在本发明的第二实施例中，多孔辊安装在化学容器和待清洁的表面之间，待清洁的表面以相对较高的速度旋转。因此，由界面多孔辊沉积在待清洗的表面上的化学物质保留在该表面的边缘，从而引起表面边缘的最佳清洁作用。污染物以这种方式从表面除去后，可以通过加入去离子水进一步清洁表面。

65. 发明授权

US06475810B1 Method of manufacturing embedded organic stop layer for dual damascene patterning 失效
标题翻译：用于双镶嵌图案的嵌入式有机停止层的制造方法
公开(公告)号：US06475810B1
公开(公告)日：2002-11-05
申请号：US09636579
申请日：2000-08-10
申请人： Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu , Simon Chooi , Yakub Aliyu
发明人： Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu , Simon Chooi , Yakub Aliyu
IPC分类号： H01L2158
CPC分类号： H01L21/76834 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76832
摘要： A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.
摘要翻译：形成双镶嵌互连结构的新方法，其中在蚀刻期间互连和电介质污染的损害最小化，在下互连上具有嵌入的有机阻挡层，并且随后用含H2的等离子体或氢自由基蚀刻有机阻挡层。

66. 发明授权

US06429122B2 Non metallic barrier formations for copper damascene type interconnects 失效
公开(公告)号：US06429122B2
公开(公告)日：2002-08-06
申请号：US09925820
申请日：2001-08-10
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831
摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

67. 发明授权

US06380084B1 Method to form high performance copper damascene interconnects by de-coupling via and metal line filling 有权
标题翻译：通过去耦合通孔和金属线填充形成高性能铜镶嵌互连的方法
公开(公告)号：US06380084B1
公开(公告)日：2002-04-30
申请号：US09678621
申请日：2000-10-02
申请人： Yeow Kheng Lim , Alex See , Cher Liang Cha , Subhash Gupta , Wang Ling Goh , Man Siu Tse
发明人： Yeow Kheng Lim , Alex See , Cher Liang Cha , Subhash Gupta , Wang Ling Goh , Man Siu Tse
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/32051 , H01L21/76802 , H01L21/76849 , H01L21/7685 , H01L21/76877 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches. A first barrier layer is deposited to line the trenches. The via trenches are filled with a first copper layer by a single deposition or by depositing a seed layer and then electroless or electrochemical plating. The first copper layer is polished down to complete the vias. A second barrier layer is deposited. The second barrier layer is patterned to form via caps. A second dielectric layer is deposited. A capping layer is deposited. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited to line the connective line trenches. The third barrier layer and the via caps are etched to form trench barrier sidewall spacers and to expose the vias. The connective line trenches are filled with a second copper layer by a single deposition, by a first deposition of a seed layer followed by plating, or by plating using the via as the seed layer. The second copper layer is polished down.
摘要翻译：已经实现了通过解耦通孔和连接线沟槽填充形成鲁棒的双镶嵌互连的方法。沉积在氮化硅层上的第一介电层。屏蔽层被沉积。将屏蔽层，第一介电层和氮化硅层图案化以形成通孔沟槽。沉积第一势垒层以对沟槽进行排列。通过单个沉积或通过沉积种子层然后进行无电镀或电化学电镀，将通孔沟槽填充有第一铜层。第一个铜层被抛光以完成通孔。沉积第二阻挡层。图案化第二阻挡层以形成通孔。沉积第二介电层。沉积覆盖层。图案化覆盖层和第二介电层以形成连接线沟槽，其暴露通孔盖的一部分。沉积第三阻挡层以对连接线沟槽进行排列。蚀刻第三阻挡层和通孔盖以形成沟槽阻挡侧壁间隔件并露出通孔。连接线沟槽通过单次沉积，通过第一次沉积种子层，然后电镀，或通过使用通孔作为种子层进行电镀，填充第二铜层。第二个铜层被抛光。

68. 发明授权

US06365508B1 Process without post-etch cleaning-converting polymer and by-products into an inert layer 失效
标题翻译：无需蚀刻后清洁 - 将聚合物和副产物转化成惰性层的方法
公开(公告)号：US06365508B1
公开(公告)日：2002-04-02
申请号：US09618264
申请日：2000-07-18
申请人： Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Xu Yi , Simon Chooi , Yakub Aliyu
发明人： Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Xu Yi , Simon Chooi , Yakub Aliyu
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76826
摘要： A new method to avoid post-etch cleaning in a metallization process is described. An insulating layer is formed over a first metal line in a dielectric layer overlying a semiconductor substrate. A via opening is etched through the insulating layer to the first metal line whereby a polymer forms on sidewalls of the via opening. The polymer is treated with a fluorinating agent whereby the polymer is converted to an inert layer. Thereafter, a second metal line is formed within the via opening wherein the inert layer acts is as a barrier layer to complete the metallization process in the fabrication of an integrated circuit device.
摘要翻译：描述了在金属化过程中避免蚀刻后清洁的新方法。在覆盖半导体衬底的电介质层中的第一金属线上形成绝缘层。通孔开口通过绝缘层蚀刻到第一金属线，由此在通孔开口的侧壁上形成聚合物。用氟化剂处理聚合物，由此将聚合物转化为惰性层。此后，在通孔开口内形成第二金属线，其中惰性层作为阻挡层，以在集成电路器件的制造中完成金属化工艺。

69. 发明授权

US06358821B1 Method of copper transport prevention by a sputtered gettering layer on backside of wafer 有权
标题翻译：通过晶片背面的溅射吸气层预防铜传输的方法
公开(公告)号：US06358821B1
公开(公告)日：2002-03-19
申请号：US09619376
申请日：2000-07-19
申请人： Subhash Gupta , Simon Chooi , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Xu Yi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono
发明人： Subhash Gupta , Simon Chooi , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Xu Yi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono
IPC分类号： H01L2122
CPC分类号： H01L21/3221 , C23C14/165 , H01L21/2885
摘要： A method of preventing copper transport on a semiconductor wafer, comprising the following steps. A semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, aluminum-copper, aluminum-silicon, and aluminum-copper-silicon is sputtered on the backside of the wafer to form a layer of metal. The back side sputtered aluminum layer may be partially oxidized at low temperature to further decrease the copper penetration possibility and to also provide greater flexibility in subsequent copper interconnect related processing. Once the back side layer is in place, the wafer can be processed as usual. The sputtered back side aluminum layer can be removed during final backside grinding.
摘要翻译：一种防止半导体晶片上的铜传输的方法，包括以下步骤。提供具有正面和背面的半导体晶片。从包括铝，铝 - 铜，铝 - 硅和铝 - 铜 - 硅的组中选择的金属溅射在晶片的背面以形成一层金属。背面溅射的铝层可以在低温下部分氧化，以进一步降低铜的渗透可能性，并且在随后的铜互连相关处理中也提供更大的灵活性。一旦背面层就位，就可以照常处理晶片。最后的背面研磨可以除去溅射的背面铝层。

70. 发明授权

US06352917B1 Reversed damascene process for multiple level metal interconnects 有权
标题翻译：用于多级金属互连的反向镶嵌工艺
公开(公告)号：US06352917B1
公开(公告)日：2002-03-05
申请号：US09598691
申请日：2000-06-21
申请人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
发明人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L21/76885 , H01L21/76801 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/76883 , H01L21/76897 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects. The patterning comprises partially etching down the damascene interconnects using a via mask overlying and protecting portions of the damascene interconnects. A trench mask also overlies and protects the first dielectric layer from metal contamination during the etching down.
摘要翻译：已经实现了在集成电路器件的制造中形成包含镶嵌互连和通孔插塞的金属互连级别的新方法。该方法创建一个反向的双镶嵌结构。第一电介质层设置在半导体衬底上。图案化电介质层以形成用于计划的大马士革互连的沟槽。可以可选地在沟槽侧壁上形成绝缘间隔物。导电阻挡层沉积在电介质层上并衬在沟槽上。沉积优选包含铜的金属层，覆盖在导电阻挡层上并填充沟槽。金属层和导电阻挡层被抛光，从而形成镶嵌互连。可以任选地沉积钝化层。大马士革互连被图案化以形成覆盖大马士革互连的通孔塞。图案化包括使用覆盖并保护大马士革互连部分的通孔掩模部分地蚀刻镶嵌互连。在蚀刻过程中，沟槽掩模也覆盖并保护第一介电层免受金属污染。

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