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61. 发明授权

US6060343A Method of forming an integrated circuit device having cyanate ester buffer coat 有权
公开(公告)号：US6060343A
公开(公告)日：2000-05-09
申请号：US257402
申请日：1999-02-25
申请人： J. Mike Brooks , Jerrold L. King , Kevin Schofield
发明人： J. Mike Brooks , Jerrold L. King , Kevin Schofield
IPC分类号： H01L21/56 , H01L23/29 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/56 , H01L23/293 , H01L2224/274 , H01L2224/48091 , H01L2224/73265 , H01L2224/854 , H01L24/48 , H01L2924/00014 , H01L2924/01039 , H01L2924/12042 , H01L2924/14 , Y10S438/902 , Y10T29/49146 , Y10T29/49171
摘要： An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.

62. 发明授权

US5903046A Integrated circuit device having cyanate ester buffer coat 失效
标题翻译：具有氰酸酯缓冲层的集成电路装置
公开(公告)号：US5903046A
公开(公告)日：1999-05-11
申请号：US604219
申请日：1996-02-20
申请人： J. Mike Brooks , Jerrold L. King , Kevin Schofield
发明人： J. Mike Brooks , Jerrold L. King , Kevin Schofield
IPC分类号： H01L21/56 , H01L23/29 , H01L23/28 , G03F7/0249
CPC分类号： H01L21/56 , H01L23/293 , H01L2224/274 , H01L2224/48091 , H01L2224/73265 , H01L2224/854 , H01L24/48 , H01L2924/00014 , H01L2924/01039 , H01L2924/12042 , H01L2924/14 , Y10S438/902 , Y10T29/49146 , Y10T29/49171
摘要： An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.
摘要翻译：一种集成电路，包括其上具有氰酸酯缓冲涂层材料的制造的模具。氰酸酯缓冲涂料包括用于进入模具的一个或多个开口。封装器件可以通过这样的开口连接到管芯接合焊盘。此外，提供一种集成电路器件，其包括制造在其上的多个集成电路的制造晶片。制造的晶片具有在制造的集成电路器件的上表面上固化的氰酸酯缓冲涂层材料的上表面。此外，制造集成电路器件的方法包括提供包括多个集成电路的制造晶片，并在制造晶片的表面上施加氰酸酯涂层材料。氰酸酯涂料的应用可以包括在制造的晶片的表面上旋转氰酸酯涂料以形成缓冲涂层。

63. 发明授权

US07005731B2 Plastic lead frames for semiconductor devices and packages including same 失效
标题翻译：用于半导体器件和包装件的塑料引线框架
公开(公告)号：US07005731B2
公开(公告)日：2006-02-28
申请号：US10801206
申请日：2004-03-16
申请人： Tongbi Jiang , Jerrold L. King
发明人： Tongbi Jiang , Jerrold L. King
IPC分类号： H01L23/495
CPC分类号： H01L24/06 , H01L21/4821 , H01L23/495 , H01L23/4951 , H01L23/49579 , H01L23/49582 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/06136 , H01L2224/2919 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/48465 , H01L2224/48599 , H01L2224/48664 , H01L2224/48699 , H01L2224/48764 , H01L2224/49175 , H01L2224/73265 , H01L2224/83101 , H01L2224/85464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/10162 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H05K3/3426 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2924/3512
摘要： A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.
摘要翻译：导电塑料引线框及其制造方法，适用于IC封装。在优选实施例中，引线框架由具有本征导电聚合物涂层的基于塑料或聚合物的引线框架结构构成。在第二实施例中，引线框架是与本征导电聚合物涂层混合的复合塑料或聚合材料。

64. 发明授权

US06841422B2 Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication 失效
标题翻译：用于半导体器件的塑料引线框架，包括其的封装以及制造方法
公开(公告)号：US06841422B2
公开(公告)日：2005-01-11
申请号：US10371672
申请日：2003-02-21
申请人： Tongbi Jiang , Jerrold L. King
发明人： Tongbi Jiang , Jerrold L. King
IPC分类号： H01L21/48 , H01L23/495 , H05K3/34 , H01L21/44 , H01L21/50
CPC分类号： H01L21/4821 , H01L23/49579 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49175 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/10162 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H05K3/3426 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.
摘要翻译：导电塑料引线框及其制造方法，适用于IC封装。在优选实施例中，引线框架由具有本征导电聚合物涂层的基于塑料或聚合物的引线框架结构构成。在第二实施例中，引线框架是与本征导电聚合物涂层混合的复合塑料或聚合材料。

65. 发明授权

US06429528B1 Multichip semiconductor package 失效
标题翻译：多芯片半导体封装
公开(公告)号：US06429528B1
公开(公告)日：2002-08-06
申请号：US09032191
申请日：1998-02-27
申请人： Jerrold L. King , Jerry M. Brooks
发明人： Jerrold L. King , Jerry M. Brooks
IPC分类号： H01L2348
CPC分类号： H01L23/4951 , H01L23/3114 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/48091 , H01L2224/4824 , H01L2224/49171 , H01L2224/73215 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： A multichip semiconductor package, and method of making is provided that has a plurality of semiconductor chips fabricated in electrical isolation one from another integrally on a singular coextensive substrate useful for numerous and varied semiconductor chip applications. The semiconductor chips, instead of being singulated into a plurality of single-chip packages, are kept as integrally formed together and are thereafter electrically connected together so as to form a larger circuit. Encapsulated follows so as to form a single, multichip package. Common signals of the plurality of semiconductor chips are bussed together in electrical common across the substrate to a common electrode suitable for electrically providing the signal to another, external circuit, such as a PWB. The common bussing is achieved by conductive leads disposed across the substrate in pair sets having an extended portion that accommodates the common electrode in contact therewith. The common electrode contacts the conductive lead through an opening formed in the encapsulant that surrounds the substrate. The extended portions of each conductive lead are staggered with respect to the extended portion of the conductive lead in the same, or juxtaposed, pair set. In this manner, multiple electrodes are available for close proximity positioning while, simultaneously, avoiding electrical shorts amongst the pair sets.
摘要翻译：提供了一种多芯片半导体封装及其制造方法，该半导体芯片具有多个半导体芯片，该半导体芯片以单独的电隔离方式整体地制造在可用于多种和多种半导体芯片应用的单一共同扩展衬底上。半导体芯片不是被单个化成多个单芯片封装，而是一体地形成在一起，然后电连接在一起形成较大的电路。封装以形成单个多芯片封装。多个半导体芯片的公共信号在基板上公共电路共同连接到适合于将信号电提供给另一个外部电路（例如PWB）的公共电极。共同的总线通过设置在跨越衬底的成对组中的导电引线实现，其具有容纳与其接触的公共电极的延伸部分。公共电极通过形成在包围衬底的密封剂中的开口接触导电引线。每个导电引线的延伸部分相对于导电引线的延伸部分以相同或并置的成对组交错。以这种方式，多个电极可用于紧密定位，同时避免对组中的电短路。

66. 发明授权

US06323543B1 Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication 失效
标题翻译：用于半导体器件的塑料引线框架，包括其的封装以及制造方法
公开(公告)号：US06323543B1
公开(公告)日：2001-11-27
申请号：US09548147
申请日：2000-04-13
申请人： Tongbi Jiang , Jerrold L. King
发明人： Tongbi Jiang , Jerrold L. King
IPC分类号： H01L23495
CPC分类号： H01L24/06 , H01L21/4821 , H01L23/495 , H01L23/4951 , H01L23/49579 , H01L23/49582 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/06136 , H01L2224/2919 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/48465 , H01L2224/48599 , H01L2224/48664 , H01L2224/48699 , H01L2224/48764 , H01L2224/49175 , H01L2224/73265 , H01L2224/83101 , H01L2224/85464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/10162 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H05K3/3426 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2924/3512
摘要： A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.
摘要翻译：一种导电塑料引线框架及其制造方法，适用于IC封装。在优选实施例中，引线框架由具有本征导电聚合物涂层的基于塑料或聚合物的引线框架结构构成。在第二实施例中，引线框架是与本征导电聚合物涂层混合的复合塑料或聚合材料。

67. 发明授权

US06258623B1 Low profile multi-IC chip package connector 有权
标题翻译：薄型多芯片芯片封装连接器
公开(公告)号：US06258623B1
公开(公告)日：2001-07-10
申请号：US09349522
申请日：1999-07-08
申请人： Walter L. Moden , Jerrold L. King , Jerry M. Brooks
发明人： Walter L. Moden , Jerrold L. King , Jerry M. Brooks
IPC分类号： H01L2144
CPC分类号： H05K1/181 , H01L25/105 , H01L2225/1029 , H01L2225/1064 , H01L2225/107 , H01L2225/1094 , H01L2924/0002 , H01L2924/3011 , H05K1/145 , H05K1/147 , H05K2201/049 , H05K2201/10515 , H05K2201/10689 , Y02P70/611 , Y10T29/49126 , Y10T29/4913 , Y10T29/49169 , H01L2924/00
摘要： A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with busses formed on one side. In another embodiment, the connector comprises multiple busses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with busses within the cage, or, alternatively, are directly fixed to leads or pads on the host circuit board.
摘要翻译：用于高速应用的低调多IC芯片封装包括用于电连接一组堆叠的初级半导体封装的等效外引线的连接器。在一个实施例中，连接器包括两部分柔性绝缘聚合物片，其一面形成有总线。在另一个实施例中，连接器包括由导电聚合物形成的多个母线。在另外的实施例中，初级封装堆叠在保持架内并使其外部引线与保持架内的总线不连接接触，或者替代地，直接固定到主电路板上的引线或焊盘。

68. 发明授权

US06233154B1 Single-piece molded module housing 有权
标题翻译：单件模制模块外壳
公开(公告)号：US06233154B1
公开(公告)日：2001-05-15
申请号：US09205872
申请日：1998-12-04
申请人： Warren M. Farnworth , Jerrold L. King
发明人： Warren M. Farnworth , Jerrold L. King
IPC分类号： H05K714
CPC分类号： H01R12/83 , H01L2224/48091 , H01L2224/48227 , H01L2924/01087 , H05K1/141 , H05K3/284 , H05K3/301 , H01L2924/00014
摘要： An adapter or housing for a module, such as a single in-line memory module (SIMM) or the like, and method of using the same are herein disclosed where the SIMM and attached housing fit a predetermined shape SIMM socket. The housing replaces SIMM board material that would otherwise be used to help secure the SIMM to a predetermined shape SIMM socket or connector. The configuration of the housing allows a SIMM or the like to be snapped or slid and secured into the housing. If desired, an adhesive, potting material and other bonding material can be used to secure the SIMM board to the housing and/or pot the SIMM within the housing.
摘要翻译：本文公开了用于模块的适配器或壳体，例如单个在线存储器模块（SIMM）等，以及其中SIMM和附接的壳体适合预定形状的SIMM插座的方法。外壳代替SIMM板材料，否则将用于帮助将SIMM固定到预定形状的SIMM插座或连接器上。壳体的构造允许SIMM等被卡扣或滑动并固定到壳体中。如果需要，可以使用粘合剂，灌封材料和其它粘合材料来将SIMM板固定到壳体内和/或将壳体内的SIMM固定。

69. 发明授权

US06207474B1 Method of forming a stack of packaged memory die and resulting apparatus 失效
标题翻译：形成堆叠的封装的存储器管芯和所产生的装置的方法
公开(公告)号：US06207474B1
公开(公告)日：2001-03-27
申请号：US09036662
申请日：1998-03-09
申请人： Jerrold L. King , Jerry M. Brooks
发明人： Jerrold L. King , Jerry M. Brooks
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L25/105 , H01L2225/06551 , H01L2225/06579 , H01L2225/06582 , H01L2225/1029 , H01L2225/1064 , H01L2225/107 , H01L2924/00014 , H01L2924/01047 , H01L2924/00 , H01L2224/48
摘要： A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a PCB board. One or more multi-conductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor devices and external circuitry. One embodiment of the multi-conductor insulating assembly includes tape (such as Kapton™ tape) on which conductors are applied. One surface of the tape is preferably adhesive so as to stick to the integrated circuit devices. When properly aligned, the conductors make contact with the terminals of the integrated circuit devices and with a multi-conductor port. There may be multiple layers of conductors where different terminals aligned in a stack are to receive different signals. Another embodiment of the multi-conductor insulating assembly includes an epoxy onto which conductors are applied. In yet another embodiment, multi-conductor insulating assembly tape is sandwiched between integrated circuit semiconductor devices. Contact pads on the tape are aligned with bond pads on the integrated circuit semiconductor devices.
摘要翻译：集成电路半导体器件的堆叠组件包括由PCB板支撑的集成电路半导体器件的堆叠。一个或多个多导体绝缘组件提供集成电路半导体器件的端子与外部电路之间的接口。多导体绝缘组件的一个实施例包括其上施加导体的带（例如Kapton TM带）。带的一个表面优选是粘合剂，以便粘附到集成电路器件。当正确对准时，导体与集成电路器件的端子和多导体端口接触。可能存在多层导体，其中不同的端子在堆叠中对齐以接收不同的信号。多导体绝缘组件的另一实施例包括在其上施加导体的环氧树脂。在另一个实施例中，多导体绝缘组装带夹在集成电路半导体器件之间。磁带上的接触焊盘与集成电路半导体器件上的接合焊盘对准。

70. 发明授权

US6153929A Low profile multi-IC package connector 有权
标题翻译：薄型多芯片封装连接器
公开(公告)号：US6153929A
公开(公告)日：2000-11-28
申请号：US138372
申请日：1998-08-21
申请人： Walter L. Moden , Jerrold L. King , Jerry M. Brooks
发明人： Walter L. Moden , Jerrold L. King , Jerry M. Brooks
IPC分类号： H01L25/10 , H01L23/02
CPC分类号： H05K1/181 , H01L25/105 , H01L2225/1029 , H01L2225/1064 , H01L2225/107 , H01L2225/1094 , H01L2924/0002 , H01L2924/3011 , H05K1/145 , H05K1/147 , H05K2201/049 , H05K2201/10515 , H05K2201/10689 , Y02P70/611 , Y10T29/49126 , Y10T29/4913 , Y10T29/49169
摘要： A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage, or, alternatively, are directly fixed to leads or pads on the host circuit board.
摘要翻译：用于高速应用的低调多IC芯片封装包括用于电连接一组堆叠的初级半导体封装的等效外引线的连接器。在一个实施例中，连接器包括两部分柔性绝缘聚合物片，其一端形成有总线。在另一个实施例中，连接器包括由导电聚合物形成的多个总线。在另外的实施例中，初级封装堆叠在保持架内并且其外引线与保持架内的总线不连接，或者替代地，直接固定到主电路板上的导线或焊盘。

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