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61. 发明授权

US08665034B2 Varactor tuning control using redundant numbering 失效
标题翻译：变容二极管调谐控制采用冗余编号
公开(公告)号：US08665034B2
公开(公告)日：2014-03-04
申请号：US13245409
申请日：2011-09-26
申请人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03B5/08
CPC分类号： H03L7/099 , H03L2207/50
摘要： Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tuning steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.
摘要翻译：公开了用于改进变容二极管电路调谐控制的技术。例如，一种装置包括用于调谐频率值的多个变容二极管。多个变容二极管包括大约sqrt（2N）变容二极管，其中N是多个调谐步骤，并且多个变容二极管的尺寸分别为1x，2x，3x，4x。。。，约为sqrt（2N）x，其中x为电容单位。 N个调谐步骤中的给定一个可以由多个组合的变容二极管表示。这可以称为冗余编号。

62. 发明授权

US08593260B2 System and method for varying response amplitude of radio transponders 有权
标题翻译：无线电转发器响应振幅变化的系统和方法
公开(公告)号：US08593260B2
公开(公告)日：2013-11-26
申请号：US12779103
申请日：2010-05-13
申请人： Han Chen , Daniel J. Friedman , Paul A. Moskowitz
发明人： Han Chen , Daniel J. Friedman , Paul A. Moskowitz
IPC分类号： H04Q5/22
CPC分类号： G06K19/0723 , G06K19/0701 , G08B13/2417
摘要： A system and method are provided for modifying the effective reading range of an radio frequency identification tag. The tag, a chip-based tag, includes an antenna and a chip in communication with the antenna. The chip includes circuitry including field effect transistors that can modify the effective reading range of the tag by modifying characteristics of the tag including the modulation depth of the backscatter signal, the impedance characteristics of the tag front end electronics, the power consumption characteristics and the threshold power-on voltage of the tag. These characteristics are change either temporarily or permanently in response to commands communicated to the tag from a radio frequency identification reader.
摘要翻译：提供了一种用于修改射频识别标签的有效读取范围的系统和方法。标签是基于芯片的标签，包括与天线通信的天线和芯片。芯片包括电路，其包括场效应晶体管，其可以通过修改标签的特性来修改标签的有效读取范围，包括反向散射信号的调制深度，标签前端电子器件的阻抗特性，功耗特性和阈值标签的上电电压。响应于从射频识别读取器传送给标签的命令，这些特征暂时或永久地改变。

63. 发明授权

US08429107B2 System for address-event-representation network simulation 有权
标题翻译：地址事件表示网络仿真系统
公开(公告)号：US08429107B2
公开(公告)日：2013-04-23
申请号：US12611968
申请日：2009-11-04
申请人： Monty M. Denneau , Daniel J. Friedman , Ralph Linsker , Mark B. Ritter
发明人： Monty M. Denneau , Daniel J. Friedman , Ralph Linsker , Mark B. Ritter
IPC分类号： G06F15/18 , G06N3/08
CPC分类号： H04L47/521
摘要： A system, method, and design structure for address-event-representation network simulation are provided. The system includes a hardware structure with a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes. To simulate each node, the hardware structure includes a source table configured to receive an input message and identify a weight associated with a source of the input message. The hardware structure also includes state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state. The hardware structure further includes a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. The hardware structure may further include learning logic configured to combine information about input messages and generated output signals, and to update weights.
摘要翻译：提供了一种用于地址事件表示网络仿真的系统，方法和设计结构。该系统包括硬件结构，其具有被配置为模拟多个互连节点的多个互连的处理模块。为了模拟每个节点，硬件结构包括被配置为接收输入消息并且识别与输入消息的源相关联的权重的源表。硬件结构还包括状态管理逻辑，其被配置为根据所识别的权重更新节点状态，并响应于更新的节点状态生成输出信号。硬件结构进一步包括目标表，其被配置为响应于输出信号产生输出消息，识别目标以接收输出消息，并发送输出消息。硬件结构还可以包括被配置为组合关于输入消息和生成的输出信号的信息并且更新权重的学习逻辑。

64. 发明授权

US08222936B2 Phase and frequency detector with output proportional to frequency difference 有权
标题翻译：相位和频率检测器，输出与频率差成比例
公开(公告)号：US08222936B2
公开(公告)日：2012-07-17
申请号：US12813828
申请日：2010-06-11
申请人： Daniel J. Friedman , Alexander V. Rylyakov , José A. Tierno
发明人： Daniel J. Friedman , Alexander V. Rylyakov , José A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/093 , H03L7/1077 , H03L7/1976
摘要： Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals.
摘要翻译：公开了相位和频率检测器和技术。例如，装置包括用于接收第一和第二时钟信号的第一电路，以及用于产生指示第一和第二时钟信号之间的相位差的至少一个信号。该装置还包括第二电路，用于接收由第一电路产生的至少一个信号，并响应于该至少一个接收信号，产生至少一个输出信号，其中与该至少一个输出信号相关的频率为与第一和第二时钟信号之间的频率差成比例。

65. 发明申请

US20120153910A1 DUAL-LOOP VOLTAGE REGULATOR ARCHITECTURE WITH HIGH DC ACCURACY AND FAST RESPONSE TIME 有权
标题翻译：具有高直流精度和快速响应时间的双环电压调节器架构
公开(公告)号：US20120153910A1
公开(公告)日：2012-06-21
申请号：US13213578
申请日：2011-08-19
申请人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
摘要翻译：双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

66. 发明授权

US08138840B2 Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control 有权
标题翻译：具有时钟抖动的数字控制振荡器的最佳抖动，用于增益和带宽控制
公开(公告)号：US08138840B2
公开(公告)日：2012-03-20
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/085 , H03L7/089
CPC分类号： H03L7/081 , H03L7/085 , H03L7/099
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译：数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。

67. 发明授权

US07916820B2 Systems and arrangements for clock and data recovery in communications 有权
标题翻译：通信中时钟和数据恢复的系统和安排
公开(公告)号：US07916820B2
公开(公告)日：2011-03-29
申请号：US11608962
申请日：2006-12-11
申请人： Hayden C. Cranford, Jr. , Daniel J. Friedman , Mounir Meghelli , Thomas H. Toifl
发明人： Hayden C. Cranford, Jr. , Daniel J. Friedman , Mounir Meghelli , Thomas H. Toifl
IPC分类号： H04L7/00
CPC分类号： H04L7/0004 , H04L7/0334
摘要： A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the CDR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.
摘要翻译：公开了一种双模式时钟和数据恢复（CDR）系统。快速锁定，过采样CDR采集模块可以开始该过程，以在启动数据采集条件下快速创建数据采集时钟信号。当从输入数据流中至少提取一些数据时，CDR系统可以指示这种稳定性，并切换到接受来自低功率CDR维护模块的控制。低功率CDR维护模块可以微调并保持数据采集信号的定时。如果CDR维护模块控制下的数据锁定质量下降到足够的程度，高功率CDR采集模块可以重新启用并重新从低功率模块重新进行控制，直到锁定质量再次足够要使用的低功耗模块。

68. 发明授权

US07791453B2 System and method for varying response amplitude of radio transponders 失效
标题翻译：无线电转发器响应振幅变化的系统和方法
公开(公告)号：US07791453B2
公开(公告)日：2010-09-07
申请号：US11562355
申请日：2006-11-21
申请人： Han Chen , Daniel J. Friedman , Paul A. Moskowitz
发明人： Han Chen , Daniel J. Friedman , Paul A. Moskowitz
IPC分类号： H04Q5/22
CPC分类号： G06K19/0723 , G06K19/0701 , G08B13/2417
摘要： A system and method are provided for modifying the effective reading range of an radio frequency identification tag. The tag, a chip based tag, includes an antenna and a chip in communication with the antenna. The chip includes circuitry including field effect transistors that can modify the effective reading range of the tag by modifying characteristics of the tag including the modulation depth of the backscatter signal, the impedance characteristics of the tag front end electronics, the power consumption characteristics and the threshold power-on voltage of the tag. These characteristics are change either temporarily or permanently in response to commands communicated to the tag from a radio frequency identification reader.
摘要翻译：提供了一种用于修改射频识别标签的有效读取范围的系统和方法。该标签是基于芯片的标签，包括与天线通信的天线和芯片。芯片包括电路，其包括场效应晶体管，其可以通过修改标签的特性来修改标签的有效读取范围，包括反向散射信号的调制深度，标签前端电子器件的阻抗特性，功耗特性和阈值标签的上电电压。响应于从射频识别读取器传送给标签的命令，这些特征暂时或永久地改变。

69. 发明申请

US20090252215A1 SAMPLED CURRENT-INTEGRATING DECISION FEEDBACK EQUALIZER AND METHOD 有权
标题翻译：采样电流一体化决策反馈均衡器和方法
公开(公告)号：US20090252215A1
公开(公告)日：2009-10-08
申请号：US12061268
申请日：2008-04-02
申请人： John F. Bulzacchelli , Timothy O. Dickson , Daniel J. Friedman , Alexander V. Rylyakov
发明人： John F. Bulzacchelli , Timothy O. Dickson , Daniel J. Friedman , Alexander V. Rylyakov
IPC分类号： H04L27/01
CPC分类号： H04L25/03019 , H04L25/03031
摘要： A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.
摘要翻译：一种判决反馈均衡器（DFE）和方法，包括耦合到输入端并包括采样保持元件的分支，所述采样保持元件被配置为从所述输入端接收和采样所接收的输入信号以及电流积分夏令。电流积分加法器与采样保持元件的输出耦合。夏天被配置为接收并且表示至少一个先前决定和输入样本的和电流。至少一个先前的决定和输入样本被集成到节点上，其中输入样本在积分期间保持不变，从而减轻输入转换对夏季输出的影响。

70. 发明授权

US07511621B1 High-performance mobile power antennas 失效
公开(公告)号：US07511621B1
公开(公告)日：2009-03-31
申请号：US11694229
申请日：2007-03-30
申请人： Dah-Weih Duan , Daniel J. Friedman , Harley Kent Heinrich , Ian Bardwell-Jones , Lou Ruggiero
发明人： Dah-Weih Duan , Daniel J. Friedman , Harley Kent Heinrich , Ian Bardwell-Jones , Lou Ruggiero
IPC分类号： G08B13/14
CPC分类号： H01Q1/2225 , G01S13/758 , G06K7/0008 , G06K19/0701 , G06K19/0713 , G06K19/0723 , H01Q1/22 , H01Q21/29
摘要： An RFID tag's mobility can be increased and cost can be decreased by using high-performance mobile power antennas instead of battery powered tags. Disclosed are some power antennas that include a half wave rectifier, a full wave rectifier, and a voltage multiplier. These antennas can be cascaded to boost the power or voltage gain. Additionally, planar elements can be added to increase efficiency without decreasing mobility.

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